Analytical Threshold Voltage Model Research Articles

Analytical modeling of threshold voltage and on-resistance in multi-barrier E-mode MISHEMT with gate-recess and field-plates

This work presents an analytical model for threshold voltage and On-resistance of multi barrier Metal–Insulator–Semiconductor High-Electron-Mobility-Transistor (MISHEMT) with gate-recess and field-plates. The device featuring a high two-dimensional electron-gas (2DEG) density in the channel region. The primary objectives of this device are to achieve a high threshold voltage (Vth) and enhance electron mobility with specific low ON-resistance (Ron_sp) by mitigating the degradation effects arising from scattering and interface-charges. Also, a physics based analytical model for Vth and 2DEG charge density at upper and lower channels is presented. This model is validated by comparing with TCAD numerical simulations and are well matched. The proposed MISHEMT demonstrates improved electron mobility in the lower channel of 1260 cm2/V.s, Vth of ∼2.6 V and Ron_sp is minimized by 33 % in contrast with a conventional MISHEMT. Additionally, the proposed MISHEMT becomes a promising device for achieving both high threshold voltage and mobility which are required for power semiconductor devices.

Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K

AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) and gm/IDS related parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.

An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET

In this work, Fourier series-based analytical models for threshold voltage (Vth) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of Vth for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm.

Physics based numerical model of a nanoscale dielectric modulated step graded germanium source biotube FET sensor: modelling and simulation

This paper proposes a novel dielectric modulated step-graded germanium source biotube FET for label-free biosensing applications. Its integrated structure and unique design combine the benefits of the gate stack, germanium source, triple-gate architecture, and a step-graded biotube channel, resulting in superior performance over existing biosensors. A compact two-dimensional analytical model for channel potential, drain current, threshold voltage, and subthreshold swing has been formulated and agrees well with the simulated results. The comprehensive investigation of different device parameters, including doping and bias, offers valuable insights into optimizing the biosensor’s performance. The proposed biosensor exhibits remarkable sensitivity, achieving up to 263 mV and 1495.52 nA for certain biomolecules, which has been validated by a compact analytical model and simulations performed on the SILVACO TCAD simulator. Several parameters are employed to assess the biosensor’s effectiveness: threshold voltage, ION/IOFF ratio, subthreshold swing, off-current, peak trans-conductance, and on-current. Furthermore, the biotube channel design enables lightweight and cost-efficient biosensors, enhancing the biosensor’s practicality. This work also includes an analysis of the effect of temperature on the biosensor’s performance and characteristics, providing insights into practical applications. High sensitivity of the biosensor signifies a significant advancement in biosensing technology, suggesting a wide range of potential applications in biomedical field.

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile

Analytical Model for Gate Capacitance and Threshold Voltage in Fin-Shaped GaN HEMTs

Fin-shaped tri-gate structure is an alternative way to achieve positive threshold voltage shift in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). This results from the combined effect of top-gate and side-gate electric fields. In this work, side-gate capacitance of fin-shaped high electron mobility transistor (fin-HEMT) is estimated using conformal mapping technique. Subsequently, a model is developed to estimate the threshold voltage of the device by incorporating this side-gate capacitance in the existing threshold formulation. This model can be included in any existing compact model framework of HEMTs to predict the threshold voltage for fin-shaped devices. The proposed model, being completely physics-based and scalable, is useful to circuit engineers for optimal design.

Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

The present article deals with the analytical modeling of threshold voltage of an ultra-thin nanotube Junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field-effect-transistor (MOSFET). Under the condition of full depletion, the modeling of the surface potential relating to inner and outer gates of the device has been performed by solving three-dimensional Poisson's equation in cylindrical coordinates with appropriate boundary conditions. Corresponding to inner and outer channel potential expressions, the two different threshold voltages of the device are obtained. Moreover, the connection between the source-to-drain subthreshold current and threshold voltage is investigated. The drain-induced-barrier-lowering (DIBL) as an indicator of short-channel effects has been studied. Further, the quantum confinement effects have been explored through quantum mechanical correction in the threshold voltage model. The model outcomes are compared with data extracted from ATLAS™ TCAD simulations, and good acceptances have been observed.

Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects

Abstract This article proposes an analytical model for channel potential and threshold voltage for negative capacitance junctionless FinFET (NC-JL FinFET). The Poisson's equation has been solved in collaboration with Landau–Khalatnikov equation to obtain analytical model for electrostatic potential distribution, threshold voltage and DIBL. The effect of fringing field on the potential distribution function due to source/drain spacer has also been taken into consideration. The results of proposed models are also validated and compared with simulated results of Sentaurus TCAD device simulator. The effect of various physical parameters like thickness of ferroelectric layer, fin thickness, spacer length, gate dielectric constant etc. on the performance of device has been studied. Further, the performance is also examined for different technology nodes and its (in context of) SCEs.

Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG SE FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions. • Impact of interface Trap Charges (ITCs) on GS-DMIG SE FD SOI MOSFET. • Analytical Modeling of Surface Potential and Threshold Voltage of GS-DMIG SE FD SOI MOSFET. • Analysis of DIBL effect at different ITC Conditions. • Comparative analysis of proposed FD SOI MOSFET in nanoscale regime. • Design and Analysis of 6T-SRAM cell using n-/p-GS-DMIG SE FD SOI with including effects of ITCs.

Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET

In this study, an analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation. The threshold voltage with channel length 50 nm was compared with the published experimental results achieved from tri-gate FinFET. Separate solutions of 2D Poisson’s equation were obtained for both symmetric and asymmetric double gate FinFET and combined using the perimeter-weighted sum approach to achieve the surface potential for TG-FinFET. The inversion charge model was used to find the threshold voltage of the above mentioned device. The results of the model were obtained for different channel lengths, fin widths and fin heights on the silicon substrate. A comparative study of hafnium dioxide (HfO2) and silicon dioxide (SiO2) for the same oxide thickness was delineated to depict the influence of the high dielectric material on the model of FinFET. As anticipated, the oxide thickness of HfO2 is greater than SiO2 to maintain the same surface potential. The result of the analytical model was well agreed with the TCAD simulation outcome. Hence, it can be considered as a promising model in device technology.

Online Junction Temperature Measurement for SiC MOSFET Based on Dynamic Threshold Voltage Extraction

The online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This article provides a potential approach for the junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFETs is approximately 5.2 mV/°C and 19.6 mV/°C, respectively.

Quantum Analytical Model for Lateral Dual Gate UTBB SOI MOSFET for Analog/RF Performance

This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field distribution, threshold voltage (Vth), surface potential and drain current (ID) have been developed and then including Quantum mechanical effects (QMEs)in it. The proposed model provides an expression for Vth shift due to QMEs, which can be used for compact modeling as a quantum correction term. The results of quantum analytical modeling have been verified with the results achieved from numerical TCAD device simulator. Different analog/ radio frequency (RF) performance parameters like transconductance (gm), output resistance (RO), transconductance generation factor (TGF), intrinsic gain (gm*RO), cut-off frequency (fT), gain bandwidth product (GBW), maximum frequency of oscillation (fmax) etc. has been investigated. The effect of negative voltage on the control gate on RF/analog performance parameters has been studied. Result reveals that the potential of UTTB SOI MOSFET with lateral dual gate becomes a choice for analog and mixed signal SOC applications.

Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

In this paper, a novel two-dimensional analytical model for threshold voltage on Dual Material Surrounding Gate Junctionless MOSFET is proposed. The analytical study is aimed at decomposing the 2-D Poisson Equations into two 1-D equations. This decomposition enables modeling of Dual Material Gates into two individual single gates. For this prospect, the Finite Differentiation Method is applied. The decomposed individual 1-D Poisson models are combined by employing relevant boundary constraints. This, in turn, provides a normal and easy solution for equation related to complex 2-D Poisson. The proposed potential model facilitates expressions of threshold voltage and sub-threshold swing. Finally, the simulation results and the analytical results were compared with the simulations obtained from TCAD which showed significant compatibility. Thus, it is defended that the proposed model illustrates the guidance regarding the designing of Dual Material Surrounding Gate Junctionless MOSFETs.

Analytical Modeling of Threshold Voltage for Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET

This paper presents, analytical modeling of surface potential,threshold voltage and DIBL for a Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET considering the parabolic approximation of surface potential. Poisson’s three-dimensional (3D) charge density equation has been solved by using proper boundary conditions to formulate the surface potential throughout the channel length. In this work, two gate metals of distinct work functions are used for gate electrode to create a step profile in channel potential. The potential step profile in surface potential reduces the SCEs in DM-DG-GAA MOSFET. The developed surface potential model is further considered to formulate the threshold voltage (Vth)model by using an effective conductive path and Fermi potential difference. The modeled threshold voltage is further used to find the Drain Induced Barrier Lowering (DIBL) effect. The threshold voltage and the DIBL are discussed with different values of device physical parameters like gate oxide (sio2) thickness, gate length ratio, channel thickness, and screening gate work function. This paper compares the SCEs of DM-DG-GAA MOSFET with Dual-Gate Gate-All-Around (DG-GAA) MOSFET and the results showing that DM-DG-GAA MOSFET offering better short channel characteristics than DG-GAA MOSFET. The model results are verified with simulation results generated from 3D device simulator ATLAS from SILVACO.

A Compact Analytical Drain Current Model of Fully Depleted SOI MOSFETs with Lightly Doped N- underneath the N+ Source Region

In this work, we report a 2-D analytical model for threshold voltage and drain current of fully depleted silicon-on-insulator (SoI) metal oxide semiconductor field-effect transistor (MOSFET) with lightly doped N- underneath the N+ source region. This model considers the effect of oxide thickness, source doping variations and silicon film thickness. The accuracy of the proposed model is verified using 2-D numerical simulations in terms of surface potential, threshold voltage and drain current. In comparison with the conventional FD SOI devices, the proposed model predicts that modified source based FD SOI structure gives better OFF-state current, improved ON-state to OFF-state current (ION/IOFF ~ 109) ratio.

Analytical 2D Modeling of Surface Potential and Threshold Voltage for Lightly Doped Substrate NMOS

Reducing the device dimensions leads to scaling of various parameters like junction depth, supply voltage and gate oxide thickness and results to the variation of threshold voltage. Threshold voltage variations can cause serious design problems. So threshold voltage can be adjusted by various ways which is the most important parameter of the MOSFET. This paper depicts the analytical modeling and simulation of Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The expression for potential at source and drain ends and threshold voltage has been derived and the theoretical values are compared with simulated values. From simulation results from SILVACO TAD tool, threshold voltage of 0.22V is achieved at a work-function of 4.12eV.

Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects

In this paper, an analytical threshold voltage model of double gate-all-around metal-oxide-semiconductorfield-effect-transistors (DGAA MOSFETs) including the fringing field effects is developed. The total fringing capacitance arising due to induced fringing fields in the device is divided into inner, outer and bottom fringing capacitance. A simple expression for each fringe capacitance is developed individually. The 3-D Poisson's equation has been solved in the channel region using the parabolic potential approximation method to develop the surface potential expressions. The effects of fringing capacitances of inner and outer gates which causes charge induction in the source/drain regions have been incorporated within the developed surface potential expressions. The change in potential due to these induced charges of source/drain region along the channel is formulated and added with the developed surface potential expression at both surfaces. The obtained modified surface potential equations have been utilized to derive the expression of the threshold voltage of the device. The performance of the proposed model has been compared with the previously developed model of DGAA MOSFET structure without High-k dielectrics. The effects of variation of device parameters on the threshold voltage have been also analyzed. The accuracy of the proposed model has been verified by numerical simulation results obtained by a device simulator VTCAD from Cogenda Int.

Analytical modeling of threshold voltage and subthreshold swing in Si/Ge heterojunction FinFET

This paper presents an analytical model of threshold voltage (Vth) and subthreshold swing (S) for a tri-gate (TG) heterojunction n-FinFET. The heterojunction is formed between the silicon source and germanium channel. The electrical parameters are analyzed by solving three-dimensional (3-D) Poisson’s equation with the aid of superposition principle. Based on the 3-D potential function and the minimum potential position in the channel, Vth and S are modeled. The model is validated against TCAD simulations. The modeled Vth and S are verified for variation of channel length (Lf), workfunction, oxide thickness (tox), drain-to-source voltage (VDS), gate-to-source voltage (VGS), channel concentration and fin width (Tfin). The models developed for Vth and S in the TG heterojunction FinFET are evaluated for its homojunction equivalent silicon structure, and found to exhibit excellent agreement with TCAD results.

A method for reduction of off state leakage current in symmetric DG JLT

A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.