Abstract
AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) and gm/IDS related parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
