Analytical Potential Model Research Articles

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

In this paper, we have developed a pseudo two-dimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor

A novel 2-D analytical potential model of source and drain region along with channel for a fully depleted symmetric double gate junction less transistor is presented in this paper. The boundary conditions for channel potential along the channel length is taken considering source and drain region and boundary conditions for source and drain potential model are derived from channel longitudinal potential expression. The potential model is validated using TCAD simulations. A method for scale length determination is also presented. Scale length expression is obtained from the transverse electrostatic potential expression. Scale length variation with silicon layer thickness and gate oxide thickness is shown. The dependence of Scale length on the dielectric constant is also shown for the three dielectrics--"$$\hbox {SiO}_2 $$SiO2", "$$\hbox {Al}_2 \hbox {O}_3 $$Al2O3" and "$$\hbox {HfO}_2 $$HfO2".

Compact Model for Nano-Wire Tunnel Field-Effect Transistor

This paper presents a compact model of the Nano-Wire Tunnel Field-Effect Transistor (NW-TFET). We analyze the validity of the previous-reported transmission probability and our model using an analytical potential model with a depletion approximation. We clarify the difference between the models by using the ratio of channel length to natural length to characterize the NW-TFET. By considering the offset of the gate voltage, the tunnel probability of our model can reproduce the numerically derived one for any channel length near the on-state. Finally, we present a compact model of the drain current.

Super-threshold semi analytical channel potential model for DG tunnel FET

In this paper, we present a physics based semi-analytical model for channel potential of symmetric double gate tunnel field effect transistor (TFET). The analytical results are compared with TCAD Sentaurus simulated data. We have used a fitting parameter $$\lambda $$?, which represents the screening length (or Debye length) of the device, in this work this fitting parameter is studied with the help of rigorous simulations. This fitting parameter will determine the I---V characteristics of the TFET device, therefore we also tried to show its behavior with changes in applied gate and drain voltages. To show the robustness of our model the results with variations in channel length and film thickness are also presented with simulated results. This model gives the RMS residual error within 0.8---5.0 % and asymptotic standard error for $$\lambda $$? within 0---4.0 % and works well for $$L_{g}\le 150$$Lg≤150 nm and $$T_{si}\ge 8$$Tsi?8 nm.

Approximate analytical channel potential model of poly-Si thin film transistors operated in the strong inversion region under the high gate and low drain biases

An approximate analytical channel potential model of polycrystalline silicon thin film transistors operated in the strong inversion region under the high gate and low drain biases is proposed. Thus, the linear relationship between the channel potential and the drain voltage is derived in the strong inversion region under the above bias condition when the polysilicon layer is ultrathin. This model agrees with the two-dimensional-device simulation results under different gate voltages, different drain voltages and different channel lengths. By comparing the relative errors between the model and the simulation results, it presents that this model is more suitable under the higher gate voltage Vg or the lower drain voltage Vd, regardless of the channel length. And this approximate analytical model is helpful in solving the two- dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

SummaryThis paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain (DMG-LDD) metal—oxide—semiconductor field-effect transistor (MOSFET) is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects (SCEs) and the drain induced barrier lowering (DIBL) more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLAS™ 2D device simulator.

2-D Analytical Model for the Threshold Voltage of a Tunneling FET With Localized Charges

In this paper, we have developed a 2-D analytical model for the surface potential and threshold voltage of a tunneling field-effect transistor (TFET) with localized charges in the oxide. These charges are generated in the oxide due to hot carrier effects in the channel. The models are derived by dividing the channel into damaged and undamaged regions and then solving the 2-D Poisson's equation in these regions. The threshold voltage is then extracted by using constant current method. The proposed models are verified by using 2-D device simulations. The model can be used to study the impact of localized charges on the threshold voltage of a TFET for varying device dimensions and charge densities and can also be utilized to design TFET-based charge trapped memory devices.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET

In this paper, we have worked out a pseudo two dimensional (2D) analytical model for surface potential and drain current of a long channel p-type Dual Material Gate (DMG) Gate All-Around (GAA) nanowire Tunneling Field Effect Transistor (TFET). The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3D device simulator Silvaco Atlas.

Deterioration Of Short Channel Effects In Dual Halo Based Triple Material Surrounding Gate (Dh-Tmsg) Mosfet

In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near source and drain ends, while the gate terminal consists of three different metals with different work functions. The results prove that the device significantly deteriorates the short channel effects which are studied by analytical model for surface potential and electric field using parabolic approximation method. The analytical results are endorsed by the simulation results.

Analytical model for surface charge property of pH-regulated nanorods

An analytical model for the zeta potential and the surface charge density of pH-regulated nanorod particles is derived for the first time. This extends existing models by taking account of the effects of multiple ionic species, surface chemistry reactions, Stern layer, and surface curvature, all of practical significance. Our model predicts excellently the experimental data in the literature for the zeta potential of 11-mercaptoundecanoic acid functionalized gold nanorod. The validated analytical multi-ion model provides valuable information for applications involving pH-tunable nanorods.

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), a better ON-state to OFF-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio, and a better subthreshold slope.

A 2-D Analytical Model for Double-Gate Tunnel FETs

This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.

Analytical model for charge properties of silica particles

An analytical model for surface charge density and zeta potential of silica particles is derived and verified. The model takes into account surface chemistry reactions of the silanol groups and multiple ionic species. The predictions are in good agreement with the experimental data available from the literature. Surface charge density and zeta potential of silica particles strongly depend on both pH and background salt concentration of the aqueous solution.

Analytical Surface Potential Model with TCAD Simulation Verification for Evaluation of Surrounding Gate TFET

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

이중게이트 MOSFET의 문턱전압이하 전류에 대한 게이트 산화막 의존성

This paper analyzed the change of subthreshold current for gate oxide thickness of double gate(DG) MOSFET. Poisson's equation had been used to analyze the potential distribution in channel, and Gaussian function had been used as carrier distribution. The potential distribution was obtained as the analytical function of channel dimension, using the boundary condition. The subthreshold current had been analyzed for gate oxide thickness, and projected range and standard projected deviation of Gaussian function. Since this analytical potential model was verified in the previous papers, we used this model to analyze the subthreshold current. Resultly, analytical model showed that subthreshold current was influenced by parameters of Gaussian function and gate oxide thickness of DGMOSFET.

Two-dimensional model of symmetrical double-gate strained Si single Halo metal-oxide semiconductor field effect transistor with gate stack dielectric

In this paper, a novel symmetrical double-gate strained Si single halo metal-oxide semiconductor field effect transistor with gate stack dielectric is proposed. The two-dimensional Poisson's equation is solved under suitable boundary condition by applying the parabolic potential approximation. This analytical model for the surface potential and the threshold voltage is derived. The strained Si channel is divided into two different doping regions, and the surface potential along the channel, compared with the normal double-gate device (uniform doping channel), exhibits a stepped potential variation, which can increase carrier transport speed. The influence of drain-source voltage on short channel effects (SCEs) is discussed. it is shown that threshold voltage decreases with Ge mole fraction increasing in butter layer, increases with the increase of the high-k layer dielectric permittivity of gate stack, and increases with the increase of doping concentration in the channel near the source, of which the physical mechanisms are analyzed and explained. Results show that the novel device can suppress threshold voltage drift and SCEs, which provides the basic guidance for designing the CMOS-based devices in nanometer scale.

Modeling of parameters for nano‐scale surrounding‐gate MOSFET considering quantum mechanical effect

In this paper, an analytical surface potential and threshold voltage model for surrounding gate metal‐oxide semiconductor field‐effect transistor are proposed considering the quantum mechanical effect (QME). Considering variable Fermi potential along the channel, a simple relation between the eigen energies and the potential energy distribution is also provided for the first time. The variation of surface potential and the threshold voltage due to QMEs are computed analytically without using any numerical iteration technique in the model. QME on drain‐induced barrier lowering and threshold voltage roll‐off are also studied to provide a more accurate model. The proposed models are compared with existing surface potential and threshold voltage models and validated by comparing with the simulated results obtained from the 2D device simulator ATLAS of Integrated Systems Engineering Technology Computer Aided Design (ISE TCAD). Very good agreement of our model with TCAD is obtained for a wide variation of device parameters. Hence, the models will aid the designing of practical surrounding gate nano‐wire transistors. Copyright © 2013 John Wiley &amp; Sons, Ltd.

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

As the MOSFET is scaled into a nanoscale regime, spreading of source/drain (S/D) dopant into the channel region will facilitate the lateral electric field spread into the channel and in turn deteriorate the gate electrostatic integrity. The short channel effects and performance are aggravated with the increase in lateral straggle (σL) of S/D Gaussian profile. In this paper, we have developed an analytical potential model that includes the effect of σL. Subsequently, an expression for threshold voltage and linear/saturation region drain current is proposed and the effect of σL over the transconductance (gm), output conductance (gds), and intrinsic gain (AV0) is studied.