Alternative Gate Dielectrics Research Articles

Ultrathin Van der Waals Lanthanum Oxychloride Dielectric for 2D Field-Effect Transistors.

Downsizing silicon-based transistors can result in lower power consumption, faster speeds, and greater computational capacity, although it is accompanied by the appearance of short-channel effects. The integration of high-mobility 2D semiconductor channels with ultrathin high dielectric constant (high-κ) dielectric in transistors is expected to suppress the effect. Nevertheless, the absence of a high-κ dielectric layer featuring an atomically smooth surface devoid of dangling bonds poses a significant obstacle in the advancement of 2D electronics. Here, ultrathin van der Waals (vdW) lanthanum oxychloride (LaOCl) dielectrics are successfully synthesized by precisely controlling the growth kinetics. These dielectrics demonstrate an impressive high-κ value of 10.8 and exhibit a remarkable breakdown field strength (Ebd ) exceeding 10 MV cm-1 . Remarkably, the conventional molybdenum disulfide (MoS2 ) field-effect transistor (FET) featuring a dielectric made of LaOCl showcases an almost negligible hysteresis when compared to FETs employing alternative gate dielectrics. This can be attributed to the flawlessly formed vdW interface and excellent compatibility established between LaOCl and MoS2 . These findings will motivate the further exploration of rare-earth oxychlorides and the development of more-than-Moore nanoelectronic devices.

Solution-processed rare-earth thulium oxide with high permittivity for low-voltage transistor and inverters applications

The use of high-permittivity (high-k) thin films as gate dielectrics is essential in the development of low-power electronics. In this work, rare-earth thulium oxide (Tm2O3) thin films were prepared by a facile solution process and annealed at various temperatures from 400 to 700 °C. The evolution of the physical and dielectric properties of Tm2O3 thin film with annealing temperature was investigated. It is demonstrated that the Tm2O3 thin film annealed at 600 °C exhibits the optimal performance, including a low leakage current of 3 × 10−10 A/cm2, a large areal capacitance of 250 nF/cm2 at 100 Hz, and a high permittivity value of 14.2. The Tm2O3 thin film as a gate insulator was integrated into the thin film transistor (TFT) employing In2O3-based semiconducting channels. The In2O3 TFT with 600 °C-annealed Tm2O3 dielectric exhibits the superior performance, with a high Ion/Ioff of 1.65 × 107, a small subthreshold swing (SS) value of 0.2 V/dec, a VTH of +1.8 V, and a mobility of 1.68 cm2/(V·s). Furthermore, an inverter constructed by connecting the TFT with a resistor exhibits full-swing characteristics. This work provides a facile and appealing method for preparing the high-k Tm2O3 thin films as alternative gate dielectrics with the potential for use in low-power electronics and logic circuit applications.

Single event burnout hardening of trench shielded power UMOSFET using High-κ dielectrics

This study proposes the High-κ dielectric Trench Shielded power UMOSFET (HK TS-UMOSFET) to be assessed using the two-dimensional numerical simulations. The simulations are employed to evaluate HK TS-UMOSFETs susceptibility to single-event burnout (SEB) mechanism. Based on the findings, the influence of alternative high permittivity gate dielectrics to silicon dioxide (SiO2) in TS-UMOSFET was discussed. Furthermore, in order to improve the performance of the device, its electrical behaviour was simulated with several high-κ dielectrics including Al2O3, Si3N4 and Aluminium Nitride (AlN). When heavy ions strike the sensitive areas of the device, the electric field distribution and SEB threshold values were extracted. Based on the values yielded, (AlN) was identified as a promising high-κ material to achieve SEB-hardened TS-UMOSFET compared to the other high-κ dielectrics. In conclusion, with (AlN), the HK TS-UMOSFET offers a high SEB tolerance and improved electrical characteristics.

(Invited) Logic Devices for Today and Tomorrow

We discuss CMOS and beyond-CMOS devices for advanced nodes of high performance technologies; from FinFETs and fully-depleted planar SOI devices of today to other fully-depleted devices of tomorrow such as gate-all-around devices (GAA) in horizontal and vertical configuration. We look at the prospects of alternative channel materials such as III-V, germanium, 2D materials and carbon nanotubes, and alternative gate dielectrics such as ferroelectrics. We also briefly discuss developments in device architectures beyond classic MOSFET, such as tunnel FETs and spin-based transport devices. Finally 3D stacking, an approach to device density improvement is also discussed. Design-technology co-optimization (DTCO) became integral and indispensable factor in formation of highly scaled technology.

Solution-Processed Rare-Earth Oxide Thin Films for Alternative Gate Dielectric Application.

Previous investigations on rare-earth oxides (REOs) reveal their high possibility as dielectric films in electronic devices, while complicated physical methods impede their developments and applications. Herein, we report a facile route to fabricate 16 REOs thin insulating films through a general solution process and their applications in low-voltage thin-film transistors as dielectrics. The formation and properties of REOs thin films are analyzed by atomic force microscopy (AFM), X-ray diffraction (XRD), spectroscopic ellipsometry, water contact angle measurement, X-ray photoemission spectroscopy (XPS), and electrical characterizations, respectively. Ultrasmooth, amorphous, and hydrophilic REO films with thickness around 10 nm have been obtained through a combined spin-coating and postannealing method. The compositional analysis results reveal the formation of RE hydrocarbonates on the surface and silicates at the interface of REOs films annealed on Si substrate. The dielectric properties of REO films are investigated by characterizing capacitors with a Si/Ln2O3/Au (Ln = La, Gd, and Er) structure. The observed low leakage current densities and large areal capacitances indicate these REO films can be employed as alternative gate dielectrics in transistors. Thus, we have successfully fabricated a series of low-voltage organic thin-film transistors based on such sol-gel derived REO films to demonstrate their application in electronics. The optimization of REOs dielectrics in transistors through further surface modification has also been studied. The current study provides a simple solution process approach to fabricate varieties of REOs insulating films, and the results reveal their promising applications as alternative gate dielectrics in thin-film transistors.

Electrical, optical, structural and chemical properties of Al2TiO5 films for high-к gate dielectric applications

In search of alternate gate dielectrics for electronic applications, aluminum titanate (Al2TiO5) thin films were deposited at room temperature by DC reactive magnetron sputtering and characterized for their structural, chemical, optical and dielectric properties. To realize the potentiality of these films for gate dielectric applications, we investigated the influence of annealing temperature on these properties. From X-ray photoelectron spectroscopic studies, it has been observed in the as-deposited films that the presence of Al3+ and Ti4+ oxidation states which correspond to Al2O3 and TiO2 respectively. After annealing at 400°C in oxygen ambient, the binding energies of Al 2p, Ti 2p and O 1s were shifted by ~1eV and it remains constant with further increase of annealing temperature from 400 to 800°C. This indicates the formation of an intermediate compound of Al2O3 and TiO2. The extracted Al, Ti and O ratio was 2:1:5 which confirms the formation of Al2TiO5. XRD studies indicate that the as-deposited films were amorphous. After annealing at 400°C, a diffraction peak (200) corresponds to aluminum titanate (Al2TiO5) started appearing, and its intensity increases with increase of annealing temperature. Metal-Oxide-Semiconductor (MOS) capacitors were fabricated and characterized to estimate the dielectric properties of the films. The as-deposited films shows high dielectric constant (к=27.0 at 100kHz) and high leakage current density values (J=0.33A/cm2 at 1MV/cm), high oxide traps (5.5×1013cm−2) and high interface state density (1.5×1013cm−2eV−1). After annealing the films show improved dielectric constant and leakage current density values. The films annealed at 600°C in oxygen ambient show better dielectric constant (к=11.2 at 100kHz) and leakage current density values (J=2.23×10−9A/cm2 at 1MV/cm), low oxide traps (1.4×1012cm−2) and low interface state density (7.1×1011cm−2eV−1) compared with the other films. This suggests that the optimum annealing temperature is required to achieve better device properties.

Investigation of high-k yttrium copper titanate thin films as alternative gate dielectrics

Nearly amorphous high-k yttrium copper titanate thin films deposited by laser ablation were investigated in both metal–oxide–semiconductor (MOS) and metal–insulator–metal (MIM) junctions in order to assess the potentialities of this material as a gate oxide. The trend of dielectric parameters with film deposition shows a wide tunability for the dielectric constant and AC conductivity, with a remarkably high dielectric constant value of up to 95 for the thick films and conductivity as low as 6 × 10−10 S cm−1 for the thin films deposited at high oxygen pressure. The AC conductivity analysis points out a decrease in the conductivity, indicating the formation of a blocking interface layer, probably due to partial oxidation of the thin films during cool-down in an oxygen atmosphere. Topography and surface potential characterizations highlight differences in the thin film microstructure as a function of the deposition conditions; these differences seem to affect their electrical properties.

Advanced CMOS Gate Stack: Present Research Progress

The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k). When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology have been a very active research area. This paper reviews the progress and efforts made in the recent years for high-k dielectrics, which can be potentially integrated into 22 nm (and beyond) technology nodes. Our work includes deposition techniques, physical characterization methods at the atomic scale, and device reliability as the focus. For most of the materials discussed here, structural and physical properties, dielectric relaxation issues, and projections towards future applications are also discussed.

High dielectric constant terbium oxide (Tb2O3) dielectric deposited on strained-Si:C

High-k Tb2O3 films deposited on strained-Si:C and treated with different post-rapid thermal annealing temperatures were formed as alternative gate dielectrics in metal oxide semiconductor devices. The dielectrics were investigated by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscopy, and electrical measurements. It was found that Tb2O3 dielectrics properly annealed at 800°C form well-crystallized Tb2O3 structures with few defects.

Enhanced Leakage Control in Scaled 45nm nMOS Devices using SiO2 and Si3N4

Gate-leakage reduction is the key motivation for the replacement of SiO2 with alternative gate dielectrics. 45nm gate length scaled grooved and bulk nMOSFETs are evaluated to bring out the most compatible and power saving dielectric option using Si3N4 and SiO2 using Silvaco ATLAS device simulator. At the scaled thickness, SiO2 controls the leakage better than Si3N4, whereas at increased thickness of the dielectric Si3N4 proves better for the field scaled grooved and bulk devices with enhanced subthreshold slopes of 51.3mv/dec and 70mv/dec respectively. The field scaled device grooved at single sharp corner may be used for HP applications whereas field scaled bulk device may be used for LP and LSTP applications. This work can be helpful to device engineers working towards achieving ultra low power applications. General Terms Low Power VLSI Design

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs

Gate-leakage current reduction is the key motivation for the replacement of traditional SiO2 gate insulator with alternative gate dielectrics. In this work, a guideline for the determination of the suitable high-k candidate was reported in the case of a SiO2/high-k gate stack in a nanoscale double-gate (DG) MOSFET. Analytical models of direct tunneling gate leakage current with SiO2 as an interfacial layer have been considered. Using these models, the most promising high-k materials for different conditions were predicted, considering the effects of equivalent oxide thickness (EOT), gate leakage current, electron effective mass, dielectric constant-k value, barrier height and interfacial oxide thickness.

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

This paper provides a novel attempt to evaluate the gate leakage and delay characteristics of CMOS transistors and logic gates with various alternative high-κ gate dielectrics, which are replacing SiO2 in traditional nanoscale MOSFETs. Results have been obtained for both fixed as well as variable loads. The assumption that all gates drive the same load is considered in order to provide a fair comparison of the effect of the variation of design and process parameters, especially that of different high-κ dielectrics on the gate direct tunnelling current and propagation delay. On the other hand, the variable loading effect considers a set of practical loading conditions for the logic gates. An exhaustive comparison of all cases finally presents concluding evidence that the tunnelling current is independent of the loading conditions. On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of integrating them into design automation tools.

Investigation of the electrical properties of the alkaline-earth oxides BaO, SrO and Ba 0.7Sr 0.3O on Si(001) as alternative gate dielectrics

We present first investigations of the electrical characteristics of high- k amorphous BaO, SrO and crystalline Ba 0.7Sr 0.3O films on n-Si(001). The MOS structures were grown in a UHV chamber on structured SiO 2 samples with Si(001) windows and were capped with Au layers afterwards for ex-situ electrical characterization. The smallest capacitance equivalent oxide thicknesses (relative to SiO 2) achieved so far in BaO, SrO and Ba 0.7Sr 0.3O MOS-diodes were 1.0, 3.5 and 1.6 nm at oxide thicknesses of 5, 10 and 10 nm, respectively. The corresponding leakage current densities at + 1 V accumulation bias were 2.1, 1.3 · 10 − 5 and 4.7 · 10 − 6 A/cm 2. The lowest interface trap densities observed at ∼ 0.2 eV below the conduction band in MOS-diodes with BaO, SrO and Ba 0.7Sr 0.3O films were 5.2 · 10 12, 9.7 · 10 11 and 9.1 · 10 10 eV − 1 cm − 2 , respectively. These results suggest that alkaline-earth oxides might be interesting materials for application as high- k gate dielectrics.

Strontium niobate high- k dielectrics: Film deposition and material properties

Strontium niobate ultrathin films were processed by water-based chemical solution deposition, an approach that offers environmental benefits. SrNb 2O 6 and Sr 2Nb 2O 7 show high- k values, which is important for applications such as alternative gate dielectrics. The study of ultrathin films (thickness <30 nm) is crucial, as this is the thickness range for the application envisaged, and as film properties depend strongly on the film thickness. SrNb 2O 6 had a lower crystallization temperature, less interfacial silicate, lower carbonate content, and higher roughness compared to Sr 2Nb 2O 7. The k values of amorphous films were limited for both compositions ( k = 12–14). Crystallization and complete removal of organics or carbonates were accomplished by high-temperature annealing, but increased the roughness and leakage current. For Sr 2Nb 2O 7, interfacial silicates were formed as well. Intermediate calcination steps improved the surface smoothness and increased the k value of SrNb 2O 6 up to 30.

Charge Conduction and Breakdown Mechanisms in Self-Assembled Nanodielectrics

Developing alternative high dielectric constant (k) materials for use as gate dielectrics is essential for continued advances in conventional inorganic CMOS and organic thin film transistors (OTFTs). Thicker films of high-k materials suppress tunneling leakage currents while providing effective capacitances comparable to those of thin films of lower-k materials. Self-assembled monolayers (SAMs) and multilayers offer attractive options for alternative OTFT gate dielectrics. One class of materials, organosilane-based self-assembled nanodielectrics (SANDs), has been shown to form robust films with excellent insulating and surface passivation properties, enhancing both organic and inorganic TFT performance and lowering device operating voltages. Since gate leakage current through the dielectric is one factor limiting continued TFT performance improvements, we investigate here the current (voltage, temperature) (I (V,T)) transport characteristics of SAND types II (pi-conjugated layer) and III (sigma-saturated + pi-conjugated layers) in Si/native SiO(2)/SAND/Au metal-insulator-metal (MIS) devices over the temperature range -60 to +100 degrees C. It is found that the location of the pi-conjugated layer with respect to the Si/SiO(2) substrate surface in combination with a saturated alkylsilane tunneling barrier is crucial in controlling the overall leakage current through the various SAND structures. For small applied voltages, hopping transport dominates at all temperatures for the pi-conjugated system (type II). However, for type III SANDs, the sigma- and pi-monolayers dominate the transport in two different transport regimes: hopping between +25 degrees C and +100 degrees C, and an apparent switch to tunneling for temperatures below 25 degrees C. The sigma-saturated alkylsilane tunneling barrier functions to reduce type III current leakage by blocking injected electrons, and by enabling bulk-dominated (Poole-Frenkel) transport vs electrode-dominated (Schottky) transport in type II SANDs. These observations provide insights for designing next-generation self-assembled gate dielectrics, since the bulk-dominated transport resulting from combining sigma- and pi-layers should enable realization of gate dielectrics with further enhanced performance.

Novel Hf and La Formamidinates for ALD Application

AbstractHfO2 is a promising dielectric for alternative high-k gate dielectrics and DRAM capacitor applications because of its high dielectric constant, excellent thermal stability and compatibility with Si processing. Particularly atomic layer deposition (ALD) is suitable as a deposition tool for gate dielectrics as well as capacitor dielectrics due to its excellent conformity and precise thickness control. In order to achieve ideal ALD performance, it is critical to have appropriate precursors. In order to achieve ideal ALD performance, it is critical to use appropriate enabling precursors. So far, Tetrakisethylmethylamidohafnium (TEMAHf) has been considered as one of the most promising precursors due to its good physical properties. However, this precursor has relatively low thermal stability, which has often become a drawback to ALD process for HfO2. To circumvent the decomposition issues of TEMAHf during ALD deposition, often low process temperatures have been used that lead to less dense films and high level of carbon contamination. In order to overcome these challenges, the novel hafnium formamidinate (Hf-FAMD) precursor is developed as an alternate Hf source at Dow Electronic Materials. Following our success with formamidinate platform in previously reported novel lanthanum formamidinate (La-FAMD) source, this new precursor also exhibits high thermal stability and high reactivity towards water and ozone. In this work, we report, for the first time, comparative studies with TEMAHf and novel Hf-FAMD source, e.g. Hf-FAMD exhibits acceptable vapor pressure (&gt; 0.1 Torr at 100 °C) similar to that of TEMAHf, and higher thermal stability than TEMAHf, thus leading to high quality ALD films. We also present the crystal structure of La-FAMD, elucidated by X-Ray Crystallography, and physical properties of novel Hf-FAMD relevant to ALD.

Composition dependence of electronic structure and optical properties of Hf1−xSixOy gate dielectrics

Composition-dependent electronic structure and optical properties of Hf1−xSixOy (0.1≤x≤0.6) gate dielectrics on Si at 450 °C grown by UV-photo-induced chemical vapor deposition (UV-CVD) have been investigated via x-ray photoemission spectroscopy and spectroscopy ellipsometry (SE). By means of the chemical shifts in the Hf 4f, Si 2p, and O 1s spectra, the Hf–O–Si bondings in the as-deposited films have been confirmed. Analyses of composition-dependent band alignment of Hf1−xSixOy/Si gate stacks have shown that the valence band (VB) offset (ΔEv) demonstrates little change; however, the values of conduction band offset (ΔEc) increase with the increase in the silicon atomic composition, resulting from the increase in the separation between oxygen 2p orbital VB state and antibonding d states intermixed of Hf and Si. Analysis by SE, based on the Tauc–Lorentz model, has indicated that decreases in the optical dielectric constant and increase in band gap have been observed as a function of silicon contents. Changes in the complex dielectric functions and band gap Eg related to the silicon concentration in the films are discussed systematically. From the band offset and band gap viewpoint, these results suggest that Hf1−xSixOy films provide sufficient tunneling barriers for electrons and holes, making them promising candidates as alternative gate dielectrics.

Effect of Rare-Earth Doping and Nitrogen Passivation Treatments on the Properties of Ultra-thin Hafnia Films

Rare-earth doped hafnia films are of great interest as higher-k dielectrics that could potentially function as alternate gate dielectrics on Si and other high-mobility semiconductor channels. We present results on the effect of nitridation on electrical and dielectric properties of hafnia films prepared by physical vapor deposition. Particular emphasis is placed on passivation of point defects by nitrogen studied through high temperature electrochemical conductivity measurements.

Growth and Characterization of Alternative Gate Dielectrics by Molecular-Beam Epitaxy

In this work, we have investigated conditions to grow epitaxial La2O3 and Sc2O3 thin films directly on (111) Si as well as epitaxial LaScO3 thin films on (100) Si using an alkaline earth oxide buffer layer. The films were structurally characterized by reflection high-energy electron diffraction (RHEED) during growth and four-circle x-ray diffraction (XRD) and high-resolution plan-view and cross-section TEM, including Z-contrast TEM after growth. The epitaxial La2O3 thin films grew with the following epitaxial relationship (0001) La2O3 // (111) Si La2O3 // [112] Si with 1 additional rotational twin variant. Sc2O3 thin films grew epitaxially with a cube-on-cube orientation relationship on (111) silicon. It was not possible to achieve epitaxial LaScO3 thin films without the use of an alkaline earth buffer layer. The epitaxial orientation relationship between the orthorhombic LaScO3 and the underlying Si was (101) LaScO3 // (001) Si and [010] LaScO3 // [110] Si.

Growth and Characterization of Alternative Gate Dielectrics by Molecular-Beam Epitaxy

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