Adiabatic Logic Research Articles

Helical Level Structure of Dirac Potential Wells.

In graphene and other massless two-dimensional Dirac materials, Klein tunneling compromises electron confinement, and momentum-space contours can be assigned a Berry phase which is either zero or π. Consequently, in such systems the energy spectrum of circular potential wells exhibits an interesting discontinuity as a function of magnetic field B: for a given angular momentum the ladder of eigen-resonances is split at an energy-dependent critical field B c. Here we show that introducing a mass term Δ in the Hamiltonian bridges this discontinuity in such a way that states below B c are adiabatically connected to states above B c whose principal quantum number differs by unity depending on the sign of Δ. In the B-Δ plane, the spectrum of these circular resonators resembles a spiral staircase, in which a particle prepared in the ∣n, m⟩ resonance state can be promoted to the ∣n± 1, m⟩ state by an adiabatic circuit of the Hamiltonian about B c, the sign depending on the direction of the circuit. We explain the phenomenon in terms of the evolving Berry phase of the orbit, which in such a circuit changes adiabatically by 2π.

Simulation of Power Measurement of Sequential Adiabatic Circuit

Simulation of Power Measurement of Sequential Adiabatic Circuit

Design and Performance Analysis of Inverter Using ECRL, MERL and PFAL

In this paper, different low energy design techniques are analyzed to overcome the shortcoming of traditional circuits. An inverter circuit is used as a reference circuits to compare three adiabatic logic designs like ECRL, MERL and PFAL. The ECRL, MERL and PFAL designed inverter circuits are simulated by using mentor graphics VLSI design software Pyxis _v10.5_5_201606075 and the obtained results are compared in terms of rise time, fall time, transistor count, delay, slew rate etc. Finally, I calculated the delays, Slew rate and other parameter of PFAL based circuit results better as compared to ECRL and MERL.

Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application

Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application

Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

This paper presents the design and the analysis of power efficient binary content addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell, but the peripheral circuits are realized by using different adiabatic logic structures. In this paper, we propose the design of 3 novel power efficient binary content addressable memory core cells (PEBCAM core cells) using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 $$\times $$? 4 were designed and implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiabatic CAM structures. The circuits were designed using 45nm CMOS technology with a sinusoidal power clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.

Degenerate eigensubspace in a triangle-level system and its geometric quantum control

The non-Abelian geometric phases appear only in a degenerate subspace and the most familiar model with such a subspace is the $N$-pod system. Here we propose an alternative system to realize a non-Abelian gauge structure. We demonstrate that a three-level system with a triangular form can have two degenerate eigenstates which can induce non-Abelian geometric phases, and notably they are the lowest eigenstates of the system. As an application of the degenerate subspace, we propose an experimentally feasible scheme to realize a universal set of quantum gates based on the adiabatic non-Abelian geometric phases. To shorten the evolution time constrained by the adiabatic condition, the shortcut to adiabaticity is adopted to speed up the adiabatic geometric quantum gates. The combination of the intrinsic geometric characteristic and shortcut to adiabaticity makes the quantum operations fast and robust against certain control errors.

Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL)

Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL)

Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic

With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.

Reversibility and energy dissipation in adiabatic superconductor logic

Reversible computing is considered to be a key technology to achieve an extremely high energy efficiency in future computers. In this study, we investigated the relationship between reversibility and energy dissipation in adiabatic superconductor logic. We analyzed the evolution of phase differences of Josephson junctions in the reversible quantum-flux-parametron (RQFP) gate and confirmed that the phase differences can change time reversibly, which indicates that the RQFP gate is physically, as well as logically, reversible. We calculated energy dissipation required for the RQFP gate to perform a logic operation and numerically demonstrated that the energy dissipation can fall below the thermal limit, or the Landauer bound, by lowering operation frequencies. We also investigated the 1-bit-erasure gate as a logically irreversible gate and the quasi-RQFP gate as a physically irreversible gate. We calculated the energy dissipation of these irreversible gates and showed that the energy dissipation of these gate is dominated by non-adiabatic state changes, which are induced by unwanted interactions between gates due to logical or physical irreversibility. Our results show that, in reversible computing using adiabatic superconductor logic, logical and physical reversibility are required to achieve energy dissipation smaller than the Landauer bound without non-adiabatic processes caused by gate interactions.

English

English

Error Suppression for Hamiltonian-Based Quantum Computation Using Subsystem Codes.

We present general conditions for quantum error suppression for Hamiltonian-based quantum computation using subsystem codes. This involves encoding the Hamiltonian performing the computation using an error detecting subsystem code and the addition of a penalty term that commutes with the encoded Hamiltonian. The scheme is general and includes the stabilizer formalism of both subspace and subsystem codes as special cases. We derive performance bounds and show that complete error suppression results in the large penalty limit. To illustrate the power of subsystem-based error suppression, we introduce fully two-local constructions for protection against local errors of the swap gate of adiabatic gate teleportation and the Ising chain in a transverse field.

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.

Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET

Novel area and energy efficient 2N-N-2P adiabatic logic with less leakage, switching noise and glitch free outputs is presented. FinFETs replace MOSFET for reduced short channel effects, lower leakage, less area and operating speeds. 2N-N-2P logic is validated using 32nm MOSFET and FinFET models and by comparison with 2N-2N2P and PFAL. FinFET circuits are compared with CMOS counterparts using benchmark inverters, Full adder, 512 inverter cascades and 4-bit CLA. The analyses also authenticate better performance under process parameter variations and demonstrate advantages of the use of FinFET for all the Evaluate, Hold and Recovery phases.

デューティ比デジタル制御法を用いたキャパシタ充電技術

An adiabatic circuit was designed for charging and discharging a supercapacitor stepwise. The duty ratio of the switching transistors is changed in a stepwise fashion and controlled by a microprocessor. The charging efficiency, that is the ratio between the work done by the power supply and electrostatic energy of the capacitor, is calculated from experimental results. The efficiency is 95% when the number of stepwise voltage is 32, which is consistent with the theoretical value.

An adiabatic charging reversible circuit with stepwise voltage control method using a microprocessor

An adiabatic circuit was designed for dissipationless charging of a capacitor. The duty ratio of the switching transistors is changed stepwise and controlled by a microprocessor. The charging efficiency, that is the ratio between the work done by the power supply and electrostatic energy of the capacitor, is calculated from experimental results. The efficiency is 94% when the number of stepwise voltage is 32, which is consistent with the theoretical value.

Energy Recovery Logic using FinFET

The performance analysis of different adiabatic logic families designed using 30nm FinFET model obtained from BSIM-CMG VerilogA model is presented in this paper. Simulations demonstrate that the circuit design using FinFET models report 12% reduction in the total average power dissipated, 11.4% reduction in switching power, 10% reduction in leakage power and 82% reduction in the total energy dissipated in comparison against its CMOS counterparts. Full custom designs have been implemented using both 32 nm CMOS PTM models and 30nm FinFET models to justifiably evaluate and compare their performance.

Low Power Combinational and Sequential Circuits with Adiabatic Complementary Pass-Transistor Logic (ACPL)

Low Power Combinational and Sequential Circuits with Adiabatic Complementary Pass-Transistor Logic (ACPL)

Parallel processing via carbon field emission-based controlled-switching of regular bijective nano systolic networks, Part II

Purpose The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced. Design/methodology/approach The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented. Findings Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented. Practical implications The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications. Originality/value The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor

A circuit for adiabatically charging and discharging a supercapacitor was designed. A microprocessor sets the duty ratio of the switching transistors that control the inductor current. Changing the duty ratio in a stepwise fashion causes the output voltage to change in a similar fashion. Stepwise voltage changes enable adiabatic charging and discharging. Current measurements showed that the eight-step charging and discharging of a supercapacitor reduced the energy dissipation to one-eighth of that for a constant-voltage process. The circuit enables precise voltage control in small steps.

Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware

Adiabatic logic is one of the circuit design techniques for designing energy-efficient hardware. In recent years, it has also been proved that this technique is suitable for designing secure hardware. In the existing literature, a Secured Quasi-Adiabatic Logic Family (SQAL) has recently been proposed in designing Differential Power Analysis (DPA)-resistant and energy-efficient hardware. SQAL shows improvement over all other existing DPA-resistant adiabatic logic in terms of energy dissipation and area-overhead. However, the drawback is, SQAL suffers from non-adiabatic energy loss during the evaluation of the outputs. To minimize the non-adiabatic loss, we propose a novel Symmetric Pass Gate Adiabatic Logic (SPGAL). SPICE simulations show that the bit-parallel cellular multiplier over GF(24) that we implemented using SPGAL saves up to 81% of energy as compared to SQAL at 12.5MHz. Calculated values of Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) show that the proposed logic gates based on SPGAL consume uniform energy for every cycle of operation irrespective of their input transition. The uniform energy rate and low power operation shows that the proposed SPGAL is energy-efficient in nature and would be resistant to DPA attack at the circuit level.