Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET

Abstract

Novel area and energy efficient 2N-N-2P adiabatic logic with less leakage, switching noise and glitch free outputs is presented. FinFETs replace MOSFET for reduced short channel effects, lower leakage, less area and operating speeds. 2N-N-2P logic is validated using 32nm MOSFET and FinFET models and by comparison with 2N-2N2P and PFAL. FinFET circuits are compared with CMOS counterparts using benchmark inverters, Full adder, 512 inverter cascades and 4-bit CLA. The analyses also authenticate better performance under process parameter variations and demonstrate advantages of the use of FinFET for all the Evaluate, Hold and Recovery phases.