Energy Recovery Logic using FinFET

Abstract

The performance analysis of different adiabatic logic families designed using 30nm FinFET model obtained from BSIM-CMG VerilogA model is presented in this paper. Simulations demonstrate that the circuit design using FinFET models report 12% reduction in the total average power dissipated, 11.4% reduction in switching power, 10% reduction in leakage power and 82% reduction in the total energy dissipated in comparison against its CMOS counterparts. Full custom designs have been implemented using both 32 nm CMOS PTM models and 30nm FinFET models to justifiably evaluate and compare their performance.