Adiabatic Logic Research Articles

Adiabatic Differential Cascode Voltage Switch Logic (A-DCVSL) for low power applications

In this paper, a new adiabatic logic family named as adiabatic differential cascode voltage-switch logic (A-DCVSL) for low power applications is presented. The family operates on a two-phase split level sinusoidal power clock instead of four-phase trapezoidal power clock. The proposed A-DCVSL circuits reduce the power dissipation by charge recovery and minimizing the peak current flow. The behavior of the inverter is analysed and the power dissipation of A-DCVSL circuit is mathematically modeled. The performance of A-DCVSL inverters is compared with other existing differential adiabatic logic families. A full subtractor is also designed to exhibit the benefits at the application level. The results confirm that the proposed A-DCVSL circuit outperforms in terms of power dissipation and can be adapted to the design of lower power applications. The simulations were performed on Tanner EDA tool using 32 nm PTM technology parameters.

Emerging trends in the developments of low power design technique

In this paper is introduced a low power design technique for developing more reliable, functional, and more cost-effective handheld cellular telephones, portable computers, and peripherals. The portability requirements of handheld computers and other portable devices have placed tremendous pressure on electronic equipment designers, who need to deal with restrictions in the size of electronic units and power consumption. Even though battery technology is continuously improving, including reduced power consumption of processors and displays, extensive and continuous use of network services aggravates these issues. Now the onus is on the research and industrial communities to extend battery life and reduce weight. Equally, research on new techniques and technologies continues, to carefully manage energy consumption in mobile devices, while still providing continuous and fast connections to services and applications. This paper also discusses the novel trends in the developments and advancements in the area of low power Very Large Scale Integration (VLSI) design, dynamic power dissipation static power loss in Complementary Metal Oxide Semiconductor (CMOS), and advanced low power technique. Though low power as a well-established domain that undergone lots of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic are elaborated.

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

Design and Analysis of Power‐Efficient Quasi‐Adiabatic Ternary Content Addressable Memory (QATCAM)

Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells are designed. The design is implemented in 180 nm complementary metal-oxide semiconductor technology with a power clock of 1.8 V on Cadence Virtuoso. It is found that the power dissipated by the proposed QATCAM cells is lower than its conventional counterparts. Adiabatic TCAM arrays are designed using adiabatic peripheral circuits. The proposed adiabatic TCAM core cells yield more considerable power savings even at higher frequencies up to 1 GHz.

A novel low power and highly efficient inverter design

The field of VLSI is evergreen and always growing. Tremendous amount of work is done to embed more gates on a given chip area. This makes it difficult to remove the generated heat. This problem can be solved by using low power circuits. Adiabatic logic style which is advancement over CMOS in terms of power dissipation is a good solution suggested by researchers. In this paper an entirely new approach is presented to address this problem. The proposed circuit dissipates least power as compared to other power saving logic styles. A comparative analysis of all the three logic styles has been presented for better understanding. The circuits are implemented and simulated on Tanner V.13 using 90 nm technology.

Energy consumption analysis of the stepwise adiabatic circuits

In this paper, an analytic model of the energy consumption of the Stepwise Adiabatic Circuits (SAC) when it is possible to discharge the load capacitor is proposed. Using this model, analytical derivations are calculated which shows us the power saving of the SACs. Using analytical derivations, the sizing of a capacitor tank is determined for a desired energy saving. For example, the derivations predict that if the sizing of the 3-step series tank capacitors is equal to the load capacitor, the power saving is 55%. Also, if the sizing of the tank is very large the energy saving of a 3-step stepwise charging is equal to 66.7%. Several Simulations in 0.18μm CMOS technology prove the accuracy of the proposed derivations.

Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function

Silicon Physical Unclonable Function (PUF) is a general hardware security primitive for security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such radio frequency identification (RFID) and wireless sensor networks (WSN), etc. In this paper, we present a design of 4-bit QUALPUF which is based on static random access memory (SRAM) for low-power portable electronic devices and then shows the post-layout simulation and measurement results. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 upmum standard CMOS process with 1.8 V supply voltage. The 4-bit QUALPUF occupies 58.7times15.7 upmu mathrm {m}^{2} of layout area. The post-layout simulation results illustrate that the uniqueness calculated from the inter-die HDs of the 4-bit QUALPUF is 47.58%, the average reliability is 95.10%, and the the energy dissipation is 29.73 fJ/cycle/bit. The functional measurement results of the fabricated chip are the same as the post-layout simulation results.

VLSI implementation of Wave Shaping Diode based Adiabatic Logic (WSDAL)

ABSTRACT This paper presents a new architecture of energy recycling for low power applications. The reported design is based on the ultra-low-power diode Based on this concept, adiabatic logic inverter, a single bit full adder, and SR flip-flop have been proposed. In this work proposed design of SR flip-flop proved the compatibility of WSDAL for sequential logic also. The proposed design of inverter recycles a greater part of power with a power delay product (PDP) of 0.041 × 10−3 aJ as compared to the latest reported adiabatic logic (2PADL) based inverter and conventional CMOS based inverter with a PDP of 0.062 × 10−3 aJ, and 0.295 × 10−3 aJ respectively at 1.8 V supply with frequency of 500 MHz. Adder realized with the proposed architecture of adiabatic logic achieves a low PDP of 3.04 × 10−3 aJ as compared to 3.52 × 10−3 aJ and 17.00 × 10−3 aJ for 2PADL adder and conventional COMS based adder respectively at a supply voltage of 1.8 V. As proof, the implemented designs have been simulated and compared based on the figure of merit (power delay product) graphically. The new designs also perform well at stringent temperature conditions and can be used for low power electronics circuits.

Implementation of parallel computing and adiabatic logic in full adder design for ultra-low-power applications

In this work, the idea of parallel computing for a full adder has been proposed. Based on parallel computing, a new architecture of full adder (A-I) has been proposed in which the input needs to pass through only two transistors to reach the output node which results in reduced delay time. The second design of full adder (A-II) has been proposed with two-phase clocked adiabatic static complementary metal oxide logic which results in decreased power dissipation. The third design of full adder (A-III) uses parallel computing for both sum and carry generation. In A-III, a buffer has been introduced to restore the logic level which proves the drive capability of parallel computing logic. The adiabatic logic-based proposed design A-II shows a 61.95% improved power delay product (PDP) as compared to the best-reported body biasing approach-based adder, whereas the fully parallel computing-based design A-III shows a 53.29% improved PDP as compared to double pass transistor-based full adder. Post layout results of the proposed design A-III verified the functionality of proposed parallel computing logic. The proposed designs also perform well under varied temperature conditions. These designs show satisfactory performance at low voltages, whereas the use of adiabatic logic makes these designs energy efficient for low power applications.

Design and Implementation of 4-Bit ALU for Low-Power using Adiabatic Logic based on FINFET

Design and Implementation of 4-Bit ALU for Low-Power using Adiabatic Logic based on FINFET

A “BILLIARDS” SIMULATION OF AN UNIVERSAL LOGIC MODULES BASED ON THE FREDKIN GATES FOR THE QUANT-UTING

In the wave of the green computing trend, research has recently intensified on the so-called adiabatic logic, reversible computing, which is supposed to be the basis of quantum computers and bring to a new level of computing power, combined with low power consumption. The basis of this logic is special reversible gates, for example, Fredkin’s gates. Reversibility is a one-to-one correspondence (bijection) between the inputs and outputs of circuits, which means, on the one hand, the possibility of total control of the results of calculations, and on the other hand, the possibility of returning the obtained "energy" quanta for the perform calculations to their source. This approach can significantly reduce the power consumption of computers, as well as increase the reliability of calculations. There are a lot of publications on this topic, however, the development of universal logic modules on such a basis has not been fully considered. The aim of the study is the development and modeling of universal logic modules based on the Fredkin element. In this case, the methods of logical synthesis of a reversible scheme based on a binary Fredkin element, modeling and analysis of billiard calculations are used. The article presents the proposed schemes of the decoder and multiplexer based on the Fredkin element, the "billiard" simulation. The practical significance of the study lies in the fact that the obtained universal logic modules can be used in the synthesis of binary reversible circuits, for example, FPGAs. The performed simulation can be used as examples in practical exercises in the discrete mathematics, mathematical logic, mathematical modeling, and circuitry disciplines.

Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic

Secure adiabatic logics are identified as the optimal solution for cryptographic modules. We previously proposed an adiabatic logic called Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic (CPO-SPGAL). The proposed CPO-SPGAL realizes a flat current waveform by considering the current path compared with conventional adiabatic logics. In this paper, to confirm more details about countermeasure against power analysis attacks, we compare S-box circuits based on the conventional and proposed adiabatic logics which are implemented using 0.18 upmu m standard CMOS. From the SPICE simulation for correlation power analysis (CPA), 409,600 power consumption traces are obtained, and the hamming distance/weight are calculated. The simulation results show that the proposed S-box is more resistant to CPA attacks than the existing adiabatic S-boxes.

Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices

Internet of Things (IoT) devices have stringent constraints on power and energy consumption. Adiabatic logic has been proposed as a novel computing platform to design energy-efficient IoT devices. Physically Unclonable Functions (PUFs) is a promising paradigm to solve security concerns such as Integrated Circuit (IC) piracy, IC counterfeiting, and the like. PUFs have shown great promise for generating the secret bits that can be used in the secure systems in an inexpensive way. However, designing a reliable PUF along with energy-efficiency is a big challenge. Therefore, for energy-efficient and reliable PUFs, we are proposing a novel energy-efficient adiabatic logic-based PUF structure. The proposed adiabatic PUF uses energy recovery concept to achieve high energy efficiency and uses the time ramp voltage to exhibit the reliable start-up behavior. The channel length of the transistors play a major role in controlling manufacturing variations. So, in this article, the circuit simulations are performed with 180nm and 45nm Complementary metal-oxide-semiconductor (CMOS) technology in a Cadence Spectre simulator to analyze the impact of channel length variations. The proposed adiabatic PUF has worst-case reliability of 96.84% and 99.6% with temperature variations at 180nm and 45nm CMOS technology, respectively. Further, the proposed adiabatic PUF consumes 1.071fJ/bit-per cycle at 180nm CMOS technology and 0.08fJ/bit-per cycle at 45nm CMOS technology.

Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics.

Directly coupled adiabatic superconductor logic

Adiabatic superconductor logic (ASL) families are energy-efficient because they can operate with a switching energy much less than the IcΦ0 product, where Ic is the critical current for Josephson junctions, Φ0 is the flux quantum, and IcΦ0 is generally on the order of 10–19 J. A switching energy of 0.03IcΦ0 has been demonstrated by adiabatic quantum-flux-parametron (AQFP) logic, which indicates the possibility of extremely energy-efficient digital circuits using ASL. ASL uses signal transformers to propagate and invert the signal current; otherwise, it is difficult to design inverters. However, signal transformers are generally difficult to miniaturize. Therefore, to realize high-density and energy-efficient superconductor circuits, ASL that does not use signal transformers is required. In this paper, we propose ASL without signal transformers, which we call directly coupled quantum-flux-parametron (DQFP). DQFP logic is based on AQFP, but it can invert signal current without using signal transformers. We conducted numerical simulation of a DQFP inverter chain to show that DQFP logic can invert signal current without signal transformers, and that DQFP logic can operate adiabatically. Then, we designed and fabricated basic DQFP circuits, such as an inverter chain and a full adder. All the circuits were found to have wide operating margins. Our results indicate that DQFP logic is suitable for high-density and energy-efficient superconductor circuits.

Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications

In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.

A comprehensive analysis on the resilience of adiabatic logic families against transient faults

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of digital systems. Nevertheless, their impact on the reliability of digital circuits due to susceptibility to soft errors has not been explored comprehensively. In this paper, we first try to survey some existing adiabatic logic families. Then we attempt to evaluate their reliability by validating their functionality under the effect of soft errors. Our evaluations which were conducted on a set of SPICE simulations have shown that amongst SCRL, 2LAL, RERL, PFAL, 2N2N2P and ECRL families the ECRL family is able to tolerate more than 90% of the injected transient faults and the applications with a high demand of reliability can use this family of adiabatic circuits. Furthermore, we will propose some suggestions for establishing reliable computations through adiabatic circuits.

Design of SRAM Cell and Array Using Adiabatic Logic

Design of SRAM Cell and Array Using Adiabatic Logic

A compact AQFP logic cell design using an 8-metal layer superconductor process

Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μA μm−2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μm × 20 μm, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.

Optimizing NMR quantum information processing via generalized transitionless quantum driving

High-performance quantum information processing requires efficient control of undesired decohering effects, which are present in realistic quantum dynamics. To deal with this issue, a powerful strategy is to employ transitionless quantum driving (TQD), where additional fields are added to speed up the evolution of the quantum system, achieving a desired state in a short time in comparison with the natural decoherence time scales. In this paper, we provide an experimental investigation of the performance of a generalized approach for TQD to implement shortcuts to adiabaticity in nuclear magnetic resonance (NMR). As a first discussion, we consider a single nuclear spin- system in a time-dependent rotating magnetic field. While the adiabatic dynamics is violated at a resonance situation, the TQD Hamiltonian is shown to be robust against resonance, allowing us to mimic the adiabatic behavior in a fast evolution even under the resonant configurations of the original (adiabatic) Hamiltonian. Moreover, we show that the generalized TQD theory requires less energy resources, with the strength of the magnetic field less than that required by standard TQD. As a second discussion, we analyze the experimental implementation of shortcuts to single-qubit adiabatic gates. By adopting generalized TQD, we can provide feasible time-independent driving Hamiltonians, which are optimized in terms of the number of pulses used to implement the quantum dynamics. The robustness of adiabatic and generalized TQD evolutions against typical decoherence processes in NMR is also analyzed.