Analog-to-digital Research Articles

Demodulation Performance Comparison of High-Speed Coherent Nyquist Pulse Signal with Analog and Digital Demultiplexing Schemes

We compare the demodulation performance of an analog OTDM demultiplexing scheme and digitized OTDM demultiplexing with an ultrahigh-speed digital signal processor in a single-channel OTDM coherent Nyquist pulse transmission. We evaluated the demodulation performance for 40, 80, and 160 Gbaud OTDM signals with a baseline rate of 10 Gbaud. As a result, we clarified that the analog scheme performs significantly better since the bandwidth for handling the demultiplexed signal is as narrow as 10 GHz regardless of the symbol rate. This enables us to use a low-speed A/D converter (ADC) with a large effective number of bits (ENOB). On the other hand, in the digital scheme, the higher the symbol rate becomes, the more bandwidth the receiver requires. Therefore, it is necessary to use an ultrahigh-speed ADC with a low ENOB for a 160 Gbaud signal. We measured the ENOB of the ultrahigh-speed ADC used in the digital scheme and showed that the measured ENOB was approximately 1.5 bits lower than that of the low-speed ADC used in the analog scheme. This 1.5-bit decrease causes a large degradation in the demodulation performance obtained with the digital demultiplexing scheme.

Development of a multifunctional real-time data processing system for interferometers on EAST

In the latest campaign of EAST experiments, two new interferometers were installed, a dispersion interferometer (DI) based on a Carbon Dioxide laser and a solid source interferometer (SSI) based on microwave multiplier sources. To make them available for the Plasma Control System (PCS) system, each of them needs to be provided with a real-time processing system to extract the detector output signal and afterward obtain the electron density information through signal processing. To obtain interferometer data quickly and reliably, a unified hardware template was applied to both interferometers. Three main parts are included in this hardware template — digitization, digital signal processing, and output modules. In particular, the digitization section uses a multi-channel Analog-to-Digital Convertor (ADC) to acquire the signals that need to be calculated. The digital signal processing part is implemented by an FPGA, which is the hardware basis of this multifunctional template that can be used for multiple interferometers. This section includes two main parts, wrapped density signal extraction and signal unwrapping. For DI it is a phase calculation based on the intensity ratio, while for SSI it is a phase calculation by means of FFT or phase demodulation. Both computational approaches form independent IP cores to build systems quickly, while these IP cores provide parameter interfaces to adapt to different application scenarios. The output module provides a variety of data transmission methods, including fiber optic transmission and Digital-Analog-Convertor (DAC) based analog transmission, to interface with PCS or other subsequent systems.This data processing system template has been applied to each of the above two interferometers and valid data were obtained in a recent EAST experiment campaign. It demonstrates the usefulness of the template and provides a reference for the design of data processing systems on future devices.

Multi-detector simultaneous sampling design in the spot-scanning defects detection system

With the decreases in semiconductor critical dimension and increases in circuit intricacy, the impact of wafer defects on the yield and manufacturing cost of integrated circuits is becoming increasingly significant. In this paper, a multimodal spot-scanning defect detection system designed for unpatterned wafer surfaces is introduced. The defect detection system's mechanics, electronics, and software are introduced, focusing on presenting a multi-detector simultaneous sampling design. The signal sampling is based on the position triggering of the rotary stage encoder. The focused illumination spot is scanned in a helical trajectory relative to the wafer in coordination with the motion of the linear stage and rotary stage. The signal detection is carried out synchronously, and the signal sampling is triggered by rotary stage encoder position pulses to achieve equally spaced sampling. The detector signals are trans-impedance amplified and transmitted differentially to transfer the analogue signals from the optical head to the main control board. Under FPGA control, the main control board completes the simultaneous sampling and signal processing through nine high-precision 16-bit SAR(successive-approximation-register) ADCs(analogue-to-digital converter) under the trigger signal. The defect detection system is designed with a pixel resolution of 4 × 4 μm, requiring a sampling position error of less than 1 pixel and an inter-channel position deviation of less than 0.1 pixel. The rotary stage prototype has a design speed of 120 rpm, and the positioning accuracy of the encoder is ±8 arcsec. Therefore, the maximum sampling position error is 1.94 μm for a 4-inch wafer sample. The maximum phase deviation between the nine channels is 32.5 ns, and the maximum position deviation is 20.4 nm.

Antenna Selections Strategies for Massive MIMO Systems With Limited-Resolution ADCs/DACs

In millimeter wave (mmWave) communication systems with massive multiple-input multiple-output (MIMO) architecture, selecting the antennas contributing most from the candidate array to transmit/receive signals is one of the effective solutions to reduce hardware cost and power consumption while maintaining high spectral efficiency. In this paper, for the communication systems where the base station (BS) equipped with massive MIMO antenna array communicates with multiple single-antenna users, the impact of limited-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) on system capacity is investigated, and two antenna selection (AS) algorithms, namely quantization-aware greedy with square maximum-volume (QAG-SMV) and group-selection (GS) schemes, are proposed to enhance system capacity for the uplink and downlink transmission, respectively. Specifically, after the quantization noise caused by limited-resolution ADCs/DACs is converted to independent additive noise, the problem of maximizing system capacity is formulated. Then, two novel AS schemes are proposed to improve system capacity. Simulation results show that the proposed AS algorithms can obtain higher average system capacity, and the computational complexity is reduced as well.

Explainable Machine Learning with Pairwise Interactions for Predicting Conversion from Mild Cognitive Impairment to Alzheimer's Disease Utilizing Multi-Modalities Data.

Predicting cognition decline in patients with mild cognitive impairment (MCI) is crucial for identifying high-risk individuals and implementing effective management. To improve predicting MCI-to-AD conversion, it is necessary to consider various factors using explainable machine learning (XAI) models which provide interpretability while maintaining predictive accuracy. This study used the Explainable Boosting Machine (EBM) model with multimodal features to predict the conversion of MCI to AD during different follow-up periods while providing interpretability. This retrospective case-control study is conducted with data obtained from the ADNI database, with records of 1042 MCI patients from 2006 to 2022 included. The exposures included in this study were MRI biomarkers, cognitive scores, demographics, and clinical features. The main outcome was AD conversion from aMCI during follow-up. The EBM model was utilized to predict aMCI converting to AD based on three feature combinations, obtaining interpretability while ensuring accuracy. Meanwhile, the interaction effect was considered in the model. The three feature combinations were compared in different follow-up periods with accuracy, sensitivity, specificity, and AUC-ROC. The global and local explanations are displayed by importance ranking and feature interpretability plots. The five-years prediction accuracy reached 85% (AUC = 0.92) using both cognitive scores and MRI markers. Apart from accuracies, we obtained features' importance in different follow-up periods. In early stage of AD, the MRI markers play a major role, while for middle-term, the cognitive scores are more important. Feature risk scoring plots demonstrated insightful nonlinear interactive associations between selected factors and outcome. In one-year prediction, lower right inferior temporal volume (<9000) is significantly associated with AD conversion. For two-year prediction, low left inferior temporal thickness (<2) is most critical. For three-year prediction, higher FAQ scores (>4) is the most important. During four-year prediction, APOE4 is the most critical. For five-year prediction, lower right entorhinal volume (<1000) is the most critical feature. The established glass-box model EBMs with multimodal features demonstrated a superior ability with detailed interpretability in predicting AD conversion from MCI. Multi features with significant importance were identified. Further study may be of significance to determine whether the established prediction tool would improve clinical management for AD patients.

Performance vs. complexity in NN pre-distortion for a nonlinear channel.

Optical communications at high bandwidth and high spectral efficiency rely on the use of a digital-to-analog converter (DAC). We propose the use of a neural network (NN) for digital pre-distortion (DPD) to mitigate the quantization and bandlimited impairments from a DAC in such systems. We experimentally validate our approach with a 64 Gbaud 8-level pulse amplitude modulation (PAM-8) signal. We examine the NN-DPD training with both direct and indirect learning methods. We compare the performance with typical Volterra, look-up table (LUT) and linear DPD solutions. We sweep regimes where nonlinear quantization becomes more prominent to highlight the advantages of NN-DPD. The proposed NN-DPD trained via direct learning outperforms the Volterra, LUT and linear DPDs by almost 0.9 dB, 1.9 dB and 2.9 dB, respectively. We find that an indirect learning recurrent NN offers better performance at the same complexity as Volterra, while a direct learning recursive NN pushes performance to a higher level than a Volterra can achieve.

Multilevel nonvolatile photomemory with long-term robust optical retention based on photoinduced depolarization

Ferroelectric memory is promising for implementing emerging information technologies, including digital storage and analog computing. Two-dimensional (2D) ferroelectric materials retain robust room-temperature ferroelectric characteristics at the single-layer limit, surpassing traditional ferroelectric materials. This characteristic enables further advancements in device miniaturization to meet the growing demand. Herein, we manufactured a metal–insulator–ferroelectric–semiconductor field-effect transistor (MIFSFET) using a 2D ferroelectric material (α-In2Se3), which displayed nonvolatile characteristics. Based on the mechanism of photoinduced depolarization in a ferroelectric semiconductor, the MIFSFET device can be used as a photomemory, capable of storing an optical image for up to 1000 s with minimal information loss and can achieve a multistate photoresponse induced by an optical pulse. Moreover, it can function as a ferroelectric memory, with an on/off ratio exceeding 106, endurance of above 3000 cycles, and stable retention. The proposed MIFSFET demonstrated excellent optical image sensing and memory functions, presenting a feasible approach for developing efficient visual systems in the future.

Study of a High-Precision Read-Out Integrated Circuit for Bridge Sensors.

Bridge sensors are widely used in military and civilian fields, and their demand gradually increases each year. Digital sensors are widely used in the military and civilian fields. High-precision and low-power analog-to-digital converters (ADCs) as sensor read-out circuits are a research hotspot. Sigma-delta ADC circuits based on switched-capacitor topology have the advantages of high signal-to-noise ratio (SNR), good linearity, and better compatibility with CMOS processes. In this work, a fourth-order feed-forward sigma-delta modulator and a digital decimation filter are designed and implemented with a correlated double sampling technique (CDS) to suppress pre-integrator low-frequency noise. This work used an active pre-compensator circuit for deep phase compensation to improve the system's stability in the sigma-delta modulator. The modulator's local feedback factor is designed to be adjustable off-chip to eliminate the effect of process errors. A three-stage cascade structure was chosen for the post-stage digital filter, significantly reducing the number of operations and the required memory cells in the digital circuit. Finally, the layout design and engineering circuit were fabricated by a standard 0.35 μm CMOS process from Shanghai Hua Hong with a chip area of 9 mm2. At a 5 V voltage supply and sampling frequency of 6.144 MHz, the modulator power consumption is 13 mW, the maximum input signal amplitude is -3 dBFs, the 1 Hz dynamic range is about 118 dB, the modulator signal-to-noise ratio can reach 110.5 dB when the signal bandwidth is 24 kHz, the practical bit is about 18.05 bits, and the harmonic distortion is about -113 dB, which meets the design requirements. The output bit stream is 24 bits.

All-analog photoelectronic chip for high-speed vision tasks

Photonic computing enables faster and more energy-efficient processing of vision data1–5. However, experimental superiority of deployable systems remains a challenge because of complicated optical nonlinearities, considerable power consumption of analog-to-digital converters (ADCs) for downstream digital processing and vulnerability to noises and system errors1,6–8. Here we propose an all-analog chip combining electronic and light computing (ACCEL). It has a systemic energy efficiency of 74.8 peta-operations per second per watt and a computing speed of 4.6 peta-operations per second (more than 99% implemented by optics), corresponding to more than three and one order of magnitude higher than state-of-the-art computing processors, respectively. After applying diffractive optical computing as an optical encoder for feature extraction, the light-induced photocurrents are directly used for further calculation in an integrated analog computing chip without the requirement of analog-to-digital converters, leading to a low computing latency of 72 ns for each frame. With joint optimizations of optoelectronic computing and adaptive training, ACCEL achieves competitive classification accuracies of 85.5%, 82.0% and 92.6%, respectively, for Fashion-MNIST, 3-class ImageNet classification and time-lapse video recognition task experimentally, while showing superior system robustness in low-light conditions (0.14 fJ μm−2 each frame). ACCEL can be used across a broad range of applications such as wearable devices, autonomous driving and industrial inspections.

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal ‘CLKSampling’ to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (fs)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the ‘CLKSampling’ signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical fs of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoMWN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum fs with all the sections of the ADC operating at 3.3 V. The FoMWN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration.

In-house data adaptation to public data: Multisite MRI harmonization to predict Alzheimer’s disease conversion

For the machine learning-based prediction of the conversion from mild cognitive impairment to Alzheimer’s disease, the collection of sufficient data to train a model is required, which involves a lot of time and expense. When data is not enough, combining public and in-house data may be appropriate by applying domain adaptation that alleviates inter-site heterogeneity. Existing methods simultaneously transform in-house and public data to represent them into a common feature space, and then train a classifier using labels in public data. However, this procedure causes the time- and cost-consuming re-training of classifier whenever in-house data changes, and also inheres the risk of information loss in public data. Motivated by this, we propose a method that only transforms in-house data while preserving public data, namely one-way domain adaptation. The proposed method represents in-house data similar with public data by matching the data distribution and the connectivity between brain regions with mean vectors and covariance matrices, respectively. Then, the pre-trained classifier in public data is applied to predict AD conversion for in-house data. The experiments, which use the Australian Imaging Biomarkers and Lifestyle Study of Aging and the Open Access Series of Imaging Studies as the in-house data and the Alzheimer's Disease Neuroimaging Initiative as the public data, show the effectiveness and efficiency of the proposed method, improving prediction performance about 34.8% on average without labels in the in-house datasets.

Expanding the Technological Possibilities of Multilayer Micro-Plasma Powder Deposition Process by Optimizing the Quality and Composition of Process Gases

Introduction. Mastering the micro-plasma powder deposition (MPWD) technology for refurbishing parts of nickel-based super alloy aircraft gas turbine engine (GTE) has been remaining a relevant task of the Ukrainian air craft industry for, at least, 15 last years.Problem Statement. MPWD or subsequent heat treatment of GTE parts made of nickel-based super alloy after long-term operating hours, with high γ'-phase content, might reveal increased cracking susceptibility. The search for ways to optimize the welding deposition technology has shown the necessity to scrutinize the positive technological effect of rational choice of the quality and content of process (shielding, plasma and transporting) gases.Purpose. To study the effect of process gas content on the heat source parameters, the conditions of the formation of deposited metal and its quality.Material and Methods. Comparative study of the micro-plasma (PPS04 plasmatron, UPNS-304M welding machine) and TIG (VSVU-315 power source) arc heat parameters depending on welding current and process gas has been conducted by the conventional flow calorimetry technology. Comparative estimation of the total work piece heat input parameters has been made based on the previously developed methodology with registering the welding current parameters based on m-DAQ14 analog-to-digital converter (ADC).Results. The comparative research during MPWD of sample parts has shown that the content and quality of process gases can significantly (up to 2.5 times) affect the amount of heat transferred into the work piece and, respectively, the possibility to provide the technological strength of “base-deposited metal” welded joint.Conclusions. The industrial MPWD process optimization by the criteria of work piece heat input parameters, technological strength of “base-deposited metal” welded joint and filler powder consumption,by means of increasing argon (plasma and transporting gas) quality by other gases impurities content and switch to 90% Ar + 10% Н2 argonhydrogen mixture shielding gas has been established to be promising and expedient way to solve the problem.

Research on attitude compensated algorithm for shipborne dynamic weighing

Shipborne dynamic weighing is fundamental in developing marine fishery resources and oceanographic research. It enables the weighing and sorting of seafood, quantitative baiting, and measurement of research sample weights in marine environments. Therefore, developing shipborne dynamic weighing systems is crucial for the integrated exploitation of marine fishery resources. However, research on shipborne dynamic weighing is limited. To address this issue, the study initially analyzed the impact of ship’s attitude information on weighing results. Subsequently, a mathematical model for shipborne dynamic weighing, incorporating compensation factors, was constructed. The compensation factors were determined using the Recursive Least Squares (RLS) method. And then real-time weight estimation was updated using Kalman filtering, effectively mitigating the influence of ship oscillations and swaying on weight measurements. Furthermore, a shipborne dynamic weighing system with a 24-bit analog-to-digital converter (ADC) and STM32F4 processor was developed. The system performance was evaluated by simulating the sail of a ship under different sea conditions on a swing platform. The results demonstrate that the average absolute percentage error of the test meets the requirement of less than 1%, and the standard deviation of the error is less than 1% F. S., which essentially meets the weight measurement requirements of marine dynamic weighing and sorting.

High-Power-Efficiency Readout Circuit Employing Average Capacitance-to-Voltage Converter for Micro-Electro-Mechanical System Capacitive Accelerometers.

A capacitance-to-voltage converter (CVC) is proposed in this paper and applied to a readout circuit for a micro-electro-mechanical system (MEMS) accelerometer to improve the power efficiency. In a traditional readout circuit, the front-end CVC has to operate at a high sampling frequency to resist thermal noise deterioration due to the large parasitic capacitance introduced by the mechanical sensing element. Thus, the back-end analog-to-digital converter (ADC) also has to operate at a high sampling frequency to avoid noise aliasing when sampling the output signal of the CVC, which leads to high power consumption. The average CVC technique is proposed in this paper to reduce the sampling frequency requirement of the back-end ADC and thus reduce the power consumption. Both the traditional readout circuit and the proposed readout circuit are simulated with a commercial 0.18 μm BCD process. The simulation results show that noise aliasing occurs, and the noise power spectral density (PSD) of the traditional readout circuit increases by 12 dB when the sampling frequency of back-end ADC is reduced by 24 dB. However, in the proposed readout circuit, a noise aliasing effect does not occur. Moreover, the proposed readout circuit reduces the power consumption by 53% without thermal noise deterioration. In addition, the proposed CVC circuits are fabricated in an 0.18 μm BCD process, and the test results show that the presented readout circuit based on the average CVC technique can obtain better performance than the traditional CVC-based readout circuit.

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a VCM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor array. Although the root-mean-square integral nonlinearity (INL) and differential nonlinearity (DNL) of the segmented capacitor array is decreased compared with the binary capacitor array at the capacitance mismatch of 1 %, the capacitor mismatch can be background calibrated and the power consumption of the digital calibration circuit is increased by only 55.4 μW under the identical calibration step condition, and there is no noticeable deterioration in the calibration speed, resulting in a significant improvement in power efficiency. In addition, a voltage-controlled oscillator (VCO)-based comparator based on the reset-in-time technique and the adaptive stage adjustment technique is employed to further reduce power consumption. Post-simulation results show that the proposed 14-bit prototype SAR ADC can enhance the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 13.35 dB and 16.72 dB respectively at a Nyquist input rate and a sampling rate of 1-MS/s. With a power supply of 1.8 V, the power consumption is 597.8 μW with a figure of merit (FoM) value of 83.3 fJ/Conv.-step in a 0.18-μm CMOS process. The total area is 0.208 mm2, of which the analog part is only 0.038 mm2.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.

On-Machine CIS SoC-Based Layerwise Inspection System for MEX Additive Manufacturing

Additive manufacturing processes build three-dimensional objects usually following a layer-upon-layer strategy. An interesting feature of this strategy is that each layer could be inspected before the next one is deposited. On-machine integration of layerwise inspection systems would not only allow for early characterization of the dimensional and geometric quality of the part, but also for the detection of intralayer defects. Contact image sensors (CIS), such as those used in desktop flatbed scanners, could be used for this purpose since they would provide bi-dimensional digital images of the whole layer and its neighborhood. CIS images combine high resolutions with a reduced acquisition time. In this work, a material extrusion (MEX) additive manufacturing system, with layerwise inspection capabilities is proposed. The system has been equipped with the CIS that Epson uses in its Perfection V39 flatbed scanner. The sensor provides two analog output signals, each one consisting on 2584 voltage levels, that represent the amount of light reflected by the material. This analog information is sent to a parallel AD converter, where an 8-bit encoding is assigned to each one of the pixels on the digitized image. To overcome microcontroller-related problems, a Zynq®-7000 system-on-chip (SoC) has been used. This SoC integrates an ARM® based processor, with the hardware programming of a field programmable gate array (FPGA). This architecture ensures an accurate and controlled readout of the various AD converters. The resultant digital image of each layer could then be then processed using different algorithms to detect defects, extract the geometry of the layer contour and characterize the dimensional and geometric quality of the object. In the example provided, a forced error consisting on 0.2 mm height local deviations, caused by a variation in extrusion temperature, was identified from 2D grayscale images obtained with the CIS sensor.

Cluster Content Caching: A Deep Reinforcement Learning Approach to Improve Energy Efficiency in Cell-Free Massive Multiple-Input Multiple-Output Networks.

With the explosive growth of micro-video applications, the transmission burden of fronthaul and backhaul links is increasing, and meanwhile, a lot of energy consumption is also generated. For reducing energy consumption and transmission delay burden, we propose a cell-free massive multiple-input multiple-output (CF-mMIMO) system in which the cache on the access point (AP) is used to reduce the load on the link. In this paper, a total energy efficiency (EE) model of a cache-assisted CF-mMIMO system is established. When optimizing EE, forming the co-operation cluster is critical. Therefore, we propose an energy-efficient joint design of content caching, AP clustering, and low-resolution digital-to-analog converter (DAC) in a cache-assisted CF-mMIMO network based on deep reinforcement learning. This scheme can effectively cache content in APs and select the appropriate DAC resolution. Then, taking into account the channel state information and user equipment (UE)'s content request preference, a deep deterministic policy gradient algorithm is used to jointly optimize the cache strategy, AP clustering, and DAC resolution decisions. Simulation results show that the energy efficiency of the proposed scheme is 4% higher than that of other schemes without the resolution optimization and is much higher than that of the only AP clustering without the joint design of content caching and channel quality.

Handheld UV spectrophotometer device for detection of methamphetamine hydrochloride based on supramolecular sensing platform

The realization of drug detection in drug-using crime sites can provide law enforcement officials with direct evidence. This research has developed and demonstrated an easy-to-use handheld sensor that can quickly detect methamphetamine (MA) in the field. The core of the handheld UV spectrophotometer device (HUVSD) is the STM32F103 series of single-chip micro-controller, which has a 32-bit microcontroller and two embedded 12-bit high-precision analog-to-digital converter (ADC) modules. Through Bluetooth-wireless transmission protocol, the spectral information can be displayed in the cell phone's app, and it is possible to visually determine whether the test sample contains methamphetamine hydrochloride substances based on the characteristic peak at 410 nm. The readily available and inexpensive inducible compound 3A and the phosphate pillar[5]arene@silver nanoparticle (PP5@AgNPs) colloidal solution were used as the reactants. The PP5@AgNPs colloidal solution and 3A were mixed and reacted at room temperature, and the color changed to gray-black. The color change was caused by the aggregation of AgNPs induced by the molecular recognition between the induction compound 3A and PP5 on the AgNPs surface. After continuing to add the drug MA, the color of the colloidal solution turned yellow again. This is due to the occurrence of competitive molecular recognition, and the interaction between PP5 and 3A/MA was investigated by molecular docking simulations. The HUVSD has high sensitivity, simple equipment, time-saving, color change visualization and suitable for on-site deployment. It only needs a Pasteur pipette, which has great potential to realize rapid on-site detection.