Multi-detector simultaneous sampling design in the spot-scanning defects detection system

Abstract

With the decreases in semiconductor critical dimension and increases in circuit intricacy, the impact of wafer defects on the yield and manufacturing cost of integrated circuits is becoming increasingly significant. In this paper, a multimodal spot-scanning defect detection system designed for unpatterned wafer surfaces is introduced. The defect detection system's mechanics, electronics, and software are introduced, focusing on presenting a multi-detector simultaneous sampling design. The signal sampling is based on the position triggering of the rotary stage encoder. The focused illumination spot is scanned in a helical trajectory relative to the wafer in coordination with the motion of the linear stage and rotary stage. The signal detection is carried out synchronously, and the signal sampling is triggered by rotary stage encoder position pulses to achieve equally spaced sampling. The detector signals are trans-impedance amplified and transmitted differentially to transfer the analogue signals from the optical head to the main control board. Under FPGA control, the main control board completes the simultaneous sampling and signal processing through nine high-precision 16-bit SAR(successive-approximation-register) ADCs(analogue-to-digital converter) under the trigger signal. The defect detection system is designed with a pixel resolution of 4 × 4 μm, requiring a sampling position error of less than 1 pixel and an inter-channel position deviation of less than 0.1 pixel. The rotary stage prototype has a design speed of 120 rpm, and the positioning accuracy of the encoder is ±8 arcsec. Therefore, the maximum sampling position error is 1.94 μm for a 4-inch wafer sample. The maximum phase deviation between the nine channels is 32.5 ns, and the maximum position deviation is 20.4 nm.