6T Cell Research Articles

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45× higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5× for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.

Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications

Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives $1.75\times $ improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves $6.48\times $ enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only $2.1\times $ larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.

Design and statistical analysis of low power and high speed 10T static random access memory cell

SummaryStatic random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub‐nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N‐controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, ‐41.6%, and 52.9% compared with 6T, NC, 10T‐sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0–1 and 1–0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static–dynamic decoder array with 20%–40% area penalty and 116%–132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

Transistor Width Effect on the Power Supply Voltage Dependence of α-SER in CMOS 6T SRAM

We present the experimental results on the impact of transistor width modulation and power supply voltage variation on the $\alpha $ -soft error rate (SER) in a 65-nm CMOS 6T static random access memory (SRAM) obtained from an accelerated test experiment using an Am- $241~\alpha $ -source. Five 6T cells with various combinations of transistor widths were tested and the results show that nMOS and pMOS widths play a different role on SER. We also found that the transistor width modulation effectiveness is highly dependent on the power supply voltage. In particular, the results show that at around nominal voltages, widening all pMOS while keeping all nMOS minimum sized, is the best way to improve SER. However, at lower voltages the results become completely different, and the best option for an overall SER improvement is to keep all transistors minimum sized.

Design of SRAM cell for low power portable healthcare applications

Biomedical applications such as body area networks (BANs) require the design of power-efficient SRAM cells for the extended battery lives of BAN sensor nodes. In this work, we have proposed a bit-interleaving supporting, robust, low-power single-ended 9T (SE9T) bitcell. Design metrics of our bitcell are compared with several bitcells such as the 7T, FD8T and SEDF9T cells for their comparative analysis. The proposed cell shows 2.87×/3.36× higher RSNM than that of 7T/FD8T and 1.05×/1.5×/7.0× higher WSNM than that of 7T/FD8T/SEDF9T, 1.15×/1.06× and 1.54×/1.38× lower distribution in TRA and IREAD, respectively, compared to 7T/FD8T. In addition, the proposed cell shows 1.15×/1.22× shorter TWA when compared to SEDF9T/7T. Furthermore, SE9T cell consumes 10.80×/17.81× lower write power than that of SEDF9T/FD8T and 1.52×/18.37× lower read power than that of 7T/FD8T. It also exhibits 1.04×/2.92× lower leakage power dissipation than that of FD8T/7T. All these developments are obtained at a cost of 2.5× longer TWA, 1.73×/1.73× longer TRA when compared to FD8T and 7T/FD8T, and 1.64×/1.06× higher write power/read power than 7T/SEDF9T @ VDD = 700 mV.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

Simulation of 6T and 8T SRAM Cell with Power Dissipation Analysis

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits plays an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect

With the increasing complexity in modern circuit designs, the 6T&6TPPNN circuits have become popular in advanced technologies for better trade-offs among routability, timing, power and performance. The 6TPPNN cells incur great challenges to layout designs, especially the legalization problem due to their complex minimum width (MW) constraints and the fragmentation effect (FE). In this paper, we address the mixed 6T&6TPPNN cell legalization problem considering both MW constraints and FE issues. Given a global placement result, we first align all cells to the correct rows/half-rows that satisfy the VDD/VSS alignment constraints, and then propose a clustering-based MW constraints solving method to eliminate all the MW violations. After that, we formulate the legalization problem with MW constraints as a quadratic programming (QP) problem, which not only satisfies the MW constraints, but also avoid causing excessive dead spaces. Finally, we integrate the FE issues into the formulated MW-aware QP model, and adopt the modulus-based matrix splitting iteration method (MMSIM) to solve the mathematical model effectively and efficiently. Experimental results show that our algorithm can resolve all MW constraints and mitigate the half-row fragmentation effect without any extra area overhead in a reasonable time.

Characterization of Half-Select Free Write Assist 9T SRAM Cell

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87×/3.37× higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40×/6.55× higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T,2.90×/2.67× and 1.06×/1.01×/5.05× narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11×/1.03× narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33× shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67×/0.31×/0.48× of the write power and 0.262×/0.605×/0.90× of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34×/0.96× of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62×/1.78× in write delay (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</sub> ) compared to 7T/SEDF9T and 1.58×/1.58× in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</sub> compared to 7T/FD8T cell at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 700 mV.

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.

7T Based SRAM Topologies with Low Power and Higher SNM

Now the era is of electronic gadgets like processors and portable devices, in which Memory plays a significant role through the usage of Static RAMs (SRAMs).Hence designing of Low power SRAM is immense for applications. But the design of SRAM is involved in higher power requirement. So there is still scope for adequate Low power Memory Array design. The Main Moto of this paper is involved in designing &amp; Simulating Low Power 16x16 SRAM Arrays using 7T SRAM cells based on Conventional, Self Controllable Voltage (SVL) &amp; Improved Self Controllable Voltage (I-SVL) methods. Also Comparative Power and SNM Analysis is carried between Conventional 7T, 7T-SVL and 7T-ISVL based Arrays. The Proposed Array using 7T Cell consumes 6.24mW which is 67.64% lesser than the Array design [2].Also I-SVL based 7T SNM is better than the SVL-7T and 7T based cell.The proposed work is carried using cadence virtuoso tool with standard library gpdk 180nm.Also Proposed Array based on I-SVL is efficient in terms of power. The proposed Cell SNM resulted in 68.57% higher in comparison with existing cell of 8T and 10T [3].

TFET-Based Robust 7T SRAM Cell for Low Power Application

TFETs have emerged as the potential candidate for future ultralow-power applications. However, the unidirectionality and poor drive current are the biggest hurdles for their deployment in static random-access memories (SRAMs), as they critically impact the write operation. In this article, first, we propose a new device structure with dual-pocket double-gate tunnel FET (DP-DGTFET) based on the earlier p-n-i-n device (SP-DGTFET). The proposed device shows improved characteristics in terms of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , and SS with comparable IOFF. The SRAM cells designed using the proposed device significantly improve the write margin (WM). The DP-DGTFET-based outward access-6T (O-6T) cell enhances the WM as high as 18× compared with its SP-DGTFET counterpart at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 0.7 V. Subsequently, a novel 7T SRAM cell is also proposed to further enhance the circuit performance particularly in terms of write-ability. The proposed cell utilizes separate read buffer and column voltage collapse write assist to enhance the read and write stabilities. We also investigate the feasibility of these pocket devices for several other configurations of SRAM cells. The proposed 7T cell designed using new dual-pocket device offers 8× higher WM, 1.3× smaller write delay, similar RSNM and read delay while consuming 2.2× smaller write power, and similar read power compared to the existing 7T cell (at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 0.5 V). The proposed cell also successfully eliminates half-selected disturb that occurs in the selected column due to voltage collapse. The proposed cell, therefore, could be a good choice for applications that demand high stability and low power requirement.

A new 7T SRAM cell in sub‐threshold region with a high performance and small area with bit interleaving capability

In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors' proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

High Stable and Low Power 8T CNTFET SRAM Cell

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications

This work presents a half-select free 12T SRAM cell with Data-Dependent Feedback Cutting approach to improve the write ability and isolated read path to enhance the read stability. The enhanced read and write ability is 1.95× and 2.84× larger respectively than that of the conventional 6T cell at 0.4 V. The half-select free behavior of proposed cell using the cross-point read/write structure facilitates the bit-interleaving memory architecture to effectively reduce the multi-bits soft error occurrence. The incorporated PMOS stacking effect in inverter pairs of the proposed cell offers the reduced leakage power which is 0.59× to that of 6T, at 0.4 V supply. To further minimize the leakage power at array level, the bit lines between two adjacent cells have been shared that consumes only 0.38× leakage power than that of the conventional 6T array for a 1 KB macro. Moreover, a Reconfigurable FPGA architecture is proposed for low power applications. The simulated static and active power consumption of 12T SRAM based reconfigurable FPGA is 0.22× and 0.45× when compared with the regular 12T FPGA. Finally, a Double Adjacent-bits Error Detection and Correction (DAEDC) scheme is suggested for the proposed bit-interleaved 12T SRAM array, to reduce the soft error effects.

Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions

Design methodology for nonvolatile SRAM (NV-SRAM) using magnetic tunnel junctions (MTJs) and architectures for improving its energy efficiency are investigated. The cell is comprised of an ordinary 6T-SRAM cell and MTJs connected to its storage nodes through additional pass transistors that enable it to electrically separate the MTJs from the 6T cell part during the normal SRAM operation mode. From the viewpoints of the stabilities (noise margins) of all the operation modes and the store currents to the MTJs with careful consideration for device process variability, the design methodology is developed. The energy efficiency is dramatically enhanced by reducing leakage currents during the normal SRAM operation and shutdown modes and by optimizing store energy to the MTJs. A newly introduced hierarchical store-free (HSF) architecture is also highly effective at improving the energy efficiency. The energy performance is computationally analyzed and experimentally verified using circuit parameters extracted from fabricated test-element-group circuits of the NV-SRAM.

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and $\text{I}_{\mathbf {on}}/\text{I}_{\mathbf {off}}$ ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices.

A design of low leakage cache memory cell for high performance processors

The noises, when augmented with leakage, destabilize the data stored in cache (SRAM). So, a novel 7T cache memory cell with reduced leakages and improved read and write performance is proposed to address the mentioned issue. The proposed cell with its unique read assist circuit provides SNM-free read operation. It also provides improved write ability by performing a differential write operation. The performance of the proposed cell is compared with the Standard-6T and Dual-VT 7T (DVT-7T) cells at 32nm technology node in the subthreshold region by SPICE simulations. The proposed structure shows significant improvement over other cells in terms of Read Static Noise Margin (RSNM), Write Static Noise Margin (WSNM), Data Retention Voltage (DRV), critical write time (Tcrit), read current (Iread) and standby leakage current (Ileak) values. In addition it uses three MOS transistor based latch structure to reduce area overhead. The Proposed-7T structure improves RSNM, WSNM, Iread and Ileak over Standard-6T cell. Similarly, performance improvement is observed in RSNM, WSNM, Iread, Tcrit(‘0’), Tcrit(‘1’) and Ileak in comparison to the DVT-7T cell. A super cut-off CMOS scheme to reduce leakages further has been employed in the paper. A process corner analysis has been done to capture the effect of process variation on the performance of cells.