Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

Abstract

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45× higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5× for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.