12-bit ADC Research Articles

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).

A 2.3-5.7 μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring.

This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO2, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 μA maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3-5.7 μW AFE power and 1.52 mm2 die area with 102dB (SpO2 mode), 110-116 dB (HR & PTT mode) dynamic range. A SpO2 test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 μW and 43.7 μW system power, respectively.

An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC

This paper presents a low-power 18/12-bit 1 MS/s reconfigurable pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC). The proposed pipelined-SAR ADC employs a two-stage SAR structure coupled through a residual amplifier, with the forestage performing 12-bit coarse quantization and the poststage handling 7-bit fine quantization, one bit of redundancy is contained in the rear stage. The input signal is sampled by the first stage, SAR ADC, using the upper plate of a capacitor array and is quantized by charge redistribution. This eliminates the need of additional DACs and subtractors, allowing direct acquisition of the residuals. In addition, the residuals can be amplified by reusing the capacitor array as a switching capacitor. To minimize static power consumption, dynamic logic is adopted in each module of the pipelined-SAR ADC. The calibration of comparator offset and capacitor mismatch is carried out using analog front-end calibration techniques. Implemented in a 180 nm CMOS process, the simulation results show an extra-low power consumption of 1.76 mW with 3.3 V supply voltage and 1 MS/s sampling rate, indicating an exceptional Schreier figure of merit (FOMs) at 181.64 dB. By shutting down the modules of the second-stage SAR ADC, the 18-bit ADC can be dynamically configured as a 12-bit ADC with a sampling rate of up to 5 MS/s.

Enhancing Electric Vehicle Charger Performance with Synchronous Boost and Model Predictive Control for Vehicle-to-Grid Integration

This paper investigates optimizing the power exchange between electric vehicles (EVs) and the grid, with a specific focus on the DC-DC converters utilized in vehicle-to-grid (V2G) systems. It specifically explores using model predictive control (MPC) in synchronous boost converters to enhance efficiency and performance. Through experiments and simulations, this paper shows that replacing diodes with SIC MOSFETs in boost converters significantly improves efficiency, particularly in synchronous mode, by minimizing the deadtime of SIC MOSFETs during switching. Additionally, this study evaluates MPC’s effectiveness in controlling boost converters, highlighting its advantages over traditional control methods. Real-world validations further validate the robustness and applicability of MPC in V2G systems. This study utilizes TMS320F28379D, one of Texas Instruments’ leading digital signal processors, enabling the implementation of MPC with a high PWM frequency of up to 200 MHz. This processor features dual 32-bit CPUs and a 16-bit ADC, allowing for high-resolution readings from sensors. Leveraging digital signal processing technologies and advanced electronic circuits, this study advances the development of high-performance boost converters, achieving power outputs of up to 48 watts and output voltages of 24 volts. Electronic circuits (PCB boards) have been devised, implemented, and evaluated to showcase their significance in advancing efficient V2G integration.

A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (VCM). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038mm2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step.

Characterization of the ATLAS Liquid Argon Front-End ASIC ALFE2 for the HL-LHC upgrade

ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution. ALFE2 is characterized using a Front-End Test Board (FETB) based on a Zynq UltraScale+ MPSoC and two octal-channel 16-bit high-speed ADCs. The test results indicate that ALFE2 fulfills or greatly exceeds all specifications on gain, noise, linearity, uniformity, and radiation tolerance.

Effect of Filters in Photoplethysmography Analog Signals Using Open-Source LTspice Software

Analog signal processing plays a crucial role in the realm of biomedical signal analysis. This study investigates the application of analog signal processing techniques in the domain of biomedical signals, focusing on enhancing the quality and reliability of recorded physiological data. The primary emphasis is on the implementation of analog filters and amplifiers to address challenges such as noise reduction, signal conditioning, and overall signal improvement. The processing of physiological signals, such as photoplethysmography (PPG), necessitates the use of amplifiers and filters within a range of 0.4 to 5Hz. Signal noise can stem from various sources, including the test subject’s muscle movement, respiration, humming, power line interference, or even from the device itself. The research methodology involves a comparison of 3 different order of Butterworth filter circuits and their impact on the signal. The test input signal is derived from an SpO$_2$ simulator, read by a standard PPG sensor, and processed by the internal 12-bit ADC of Nucleo-F429ZI. The resulting data is stored in CSV format for subsequent use in filter design simulations with SPICE. For analog circuit designers, the utilization of SPICE in the form of LTspice proves invaluable. This open software, LTspice, boasts a simple yet powerful interface, facilitating a focus on the conceptualization and performance of the design

A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 μm. Measurement results illustrated a power consumption of 30.7 μW (analog power: 16.1 μW and digital power: 14.6 μW), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step.

A 28.9–38.8 μW dual-mode 10-bit column parallel single-slope ADC with minimum voltage feedback for CMOS image sensors

A dual-mode low-power column parallel single-slope (SS) ADC incorporating Minimum Voltage Feedback (MVF) is proposed for CMOS image sensors. When it works in low-power mode, the ADC utilizes a minimum voltage feedback approach and a dynamic bias structure to minimize the power consumption after the ramp signal surpasses the minimum voltage of a row. In its acceleration mode, it uses the minimum voltages extracted by the MVF circuit to improve the conversion speed. A 10-bit SS ADC with MVF was designed in a 0.18 μm CMOS process. The simulations have been performed to validate the proposed idea. The simulation results show that DNL and INL of the ADC are +0.124/-0.126 LSB and +0.15/-0.12 LSB, respectively. Moreover, the SNDR achieves 61.4 dB, the SFDR is 72.04 dB and the ENOB is 9.9 bit. Under the clock frequency of 100 MHz and the power supply of 3.3 V/1.8 V in the low-power mode, the simulated power consumption of the ADC ranges between 28.9 and 38.8 μW/column, with the column parallel comparator and ramp generator contributing to power reductions of up to 33.0 % and 53.5 %, respectively. The conversion time experiences a notable decrease of up to 65.4 % in the acceleration mode. The power consumption of the added MVF circuit is only 0.15 μW/column.

Smart Soil Moisture Control Based on IoT ESP-32 for Horticulture Cultivation in Coastal Area

Optimal and effective use of water in coastal areas is an essential aspect of plant growth in horticulture and the maintenance of water availability. It is necessary to monitor soil moisture continuously as the basis for watering time. However, it is hard for farmers to be in the field frequently to monitor the land humidity, even using an instrument to measure it at the site. It is needed a monitoring technique that can control the land humidity remotely. This paper presents a design of wireless soil moisture measurement based on the Internet of Things. We applied capacitive soil moisture sensors coupled with an ESP32 WIFI with a built-in 12-bit ADC function for reading analog sensor output and establishing a wireless connection to the internet network. The ESP32 was programmed using Arduino software. We made a web-based user interface and Google spreadsheet application using the Nodered which is a programmable IoT platform to show soil moisture and control the irrigation sprayers through the pump.

Development of low cost pyranometer IoT based solar irradiance measurement station

This paper presents the design of self-sustainable IoT pyranometer station using low cost BPW34 photodiode. The sustainable power of the station is achieved by a 20W solar panel charges a 7.2Ah lead acid battery through a charge controller. This station uses low cost BPW34 sensors which are connected to a 16-bit ADC module to convert the analog voltage into digital data. This module is connected to an ESP32 microcontroller that connects to Wi-Fi and sends sensor readings to ThingSpeak IoT platform to allow monitoring. This study collected over 36000 data points throughout February 2023 with an average daily data loss of 2.47%. Polynomial regression method was used to determine a best fit curve equation between the BPW34 sensor and the reference sensor. The result shows that the proposed BPW34 sensor achieve the highest error of ±80W/m2 with approximate 3% of daily data. The summary, a second order polynomial equation is found best fit for the proposed low cost BPW34 sensor.

Design and development of MTCA.4-based generic control and data acquisition module for CSNS-II and SAPS-TP

A new generation of domestically generic control and data acquisition AMC module has been developed to meet the requirements of the upgrade and renovation of the RCS LLRF system in the CSNS-II project, as well as the horizontal testing needs of the SAPS-TP. This module complies with the MicroTCA.4 standard and utilizes the Xilinx ZYNQ 7045 SOC as the core data processing chip. It can simultaneously run FPGA algorithms and the EPICS IOC remote control application program, serving as an autonomous control node. The module is equipped with 8 channels of 125 MSPS 16-bit ADC and 2 channels of 16-bit DAC with a maximum sampling rate of up to 500 MSPS. It also features standard expansion interface, front optical panel fiber interface, external clock interface, front panel digital IO interface, and more, catering to the needs of multiple systems in accelerator facilities such as radio-frequency, beam diagnostics, and control system. Additionally, the module can function independently for smaller-scale experimental and testing systems, such as the LLRF system for horizontal testing of SAPS-TP. To guarantee the seamless integration and proper operation of the AMC module within the MicroTCA.4 ecosystem, the MMC mezzanine card has been developed and thoroughly tested. In order to further reduce costs for small-scale systems, we optimized the software of the MMC so that the AMC board can run without the MCH module and realize self-health monitoring. For common applications, we have developed a complete software architecture and demo programs, including FPGA firmware, embedded Linux operating system, kernel driver modules, and EPICS IOC demo application programs. Detailed measurements have been conducted on hardware performance such as SNR, SFDR, channel isolation, as well as software performance including AXI DMA data bandwidth and system resources utilization, etc. The measurement results indicate that the module's performance indicators meet the design requirements.

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC.The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW.The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications.

A SAR ADC for multichannel synchronous signal acquisition

A synchronous sampling multichannel ADC is proposed to sample several signals at the same time and digitize the sampled signals in sequence. Instead of using multiple ADCs or multiple samplers, a modified SAR ADC with multiple capacitive DACs is applied to largely save area and reduce gain and offset mismatches between channels. A common-mode voltage resampling technique is proposed to reduce crosstalk errors between the multiple input signals below the ADC noise floor. To verify the ADC structure, a 10-bit 4-channel SAR ADC has been prototyped and implemented with a 180-nm CMOS technology. The ADC area is 0.325 mm2 (without PAD). At the sampling frequency of 250 kHz per channel, it uses 62 μW to achieve 9.38 ENOB for four input signals. The resolutions of the four channels are mainly limited by the DAC performances.

SpacePix3: SOI MAPS detector for space radiation monitoring

The SpacePix3 monolithic active pixel sensor is a novel ASIC for space radiation monitoring designed in a 180 nm SOI CMOS technology. The detector is capable of detecting and differentiating protons, electrons, and heavy ions. Its active sensor area is 3.84×3.84 mm2, pixel matrix is arranged in a 64×64 square array with 60 µm pitch. The pixel front-end amplifier signal range is 1–80 ke-, extended up to 30 Me- using a backside channel. Diodes integrated in the handle wafer in each pixel are biased at -150 V, creating a depleted layer approximately 35 µm deep. Impinging particle generates a charge pulse converted to a voltage pulse by the charge-sensitive amplifier. Maximum voltage memorized by the peak detector hold circuit is digitized using on-chip 10-bit asynchronous column SAR ADCs. Two readout interfaces are available, 400 MHz LVDS and 50 MHz SPI. Total current consumption is 31 mA from a 1.8 V power supply in the SPI mode.

Analysis and design of a new shift monotonic switching procedure for SAR ADC

A New Shift Monotonic Switching (NSMS) DAC capacitor array switching scheme suitable for successive approximation register Analog-to-Digital Converters (SAR ADCs) is proposed. The proposed DAC switching scheme utilizes two DAC arrays to achieve double-swing input signals without increasing the size of the capacitor array. In this paper, a 10-bit SAR ADC behavioral-level model is established through detailed analysis of the previously proposed energy-efficient DAC capacitor array switching scheme and the proposed NSMS switching scheme. Compared to the merged capacitor switching (MCS) scheme, the proposed NSMS switching scheme achieves an average switching energy optimization of 88% while maintaining better linearity. Additionally, for low-sampling-frequency applications, an improved SAR ADC architecture based on the NSMS capacitor array switching scheme is provided, which further reduces power consumption and system overhead.

Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.

Improving Reading Accuracy of ACS712 Current Sensor with ATmega328 10-Bit ADC: Enhancing Resolution to 5Ma/BIT via AD620 Differential Amplifier and Kalman Filters

The study focuses on the development of a current measuring device that incorporates the ACS712 current sensor, enhances the reading sensitivity of the ACS712 current sensor from 27mA/bit to 5mA/bit through the implementation of an AD620 differential amplifier, and employs a Kalman filter for improved accuracy. This increase in current uses a differential amplifier AD620. An increase in the sensitivity of the reading is carried out by utilizing the initial value of the ACS712 sensor when it has not been connected to the circuit or an offset of 512 to 0 so that 10bit ADC data can be utilized to measure 4880 mV/A so that the accuracy of reading 1-bit data is equal to 4, 8 mV/mA after being given a gain of 26.5 times. The signal enhanced from the AD620 will be filtered using the Kalman filter program so that the signal generated after the increase will be stable, and the current value that has been read will be displayed on the LCD screen. Based on the analysis results, the ACS712 current sensor can effectively measure up to 5mA/bit stably using the AD620 differential amplifier and Kalman filter.

A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors

This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC). The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section decision, 4-bit coarse conversion, and finally 8-bit fine conversion with 1-bit redundancy. The conversion step is substantially reduced from conventional 4096 to 276. The linearity of the ADC is guaranteed by a stable common mode voltage of the comparator varying only within 31.25 mV. Moreover, two high-accuracy ramp calibration techniques are utilized to correct the current variation in the fine ramp and the slope error between the coarse and fine ramps. A hybrid comparator is utilized in the ADC to save power while maintaining the performance. The ADC is designed and simulated in 0.18 μm CMOS process with 7.5 μm width. The differential nonlinearity and integral nonlinearity of the proposed ADC are reduced from +0.3/-1 LSB and +3.1/-2.55 LSB to +0.3/-0.3 LSB and +1/-0.45 LSB at 61.7 kS/s sample rate by the calibrations.