An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC

Abstract

This paper presents a low-power 18/12-bit 1 MS/s reconfigurable pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC). The proposed pipelined-SAR ADC employs a two-stage SAR structure coupled through a residual amplifier, with the forestage performing 12-bit coarse quantization and the poststage handling 7-bit fine quantization, one bit of redundancy is contained in the rear stage. The input signal is sampled by the first stage, SAR ADC, using the upper plate of a capacitor array and is quantized by charge redistribution. This eliminates the need of additional DACs and subtractors, allowing direct acquisition of the residuals. In addition, the residuals can be amplified by reusing the capacitor array as a switching capacitor. To minimize static power consumption, dynamic logic is adopted in each module of the pipelined-SAR ADC. The calibration of comparator offset and capacitor mismatch is carried out using analog front-end calibration techniques. Implemented in a 180 nm CMOS process, the simulation results show an extra-low power consumption of 1.76 mW with 3.3 V supply voltage and 1 MS/s sampling rate, indicating an exceptional Schreier figure of merit (FOMs) at 181.64 dB. By shutting down the modules of the second-stage SAR ADC, the 18-bit ADC can be dynamically configured as a 12-bit ADC with a sampling rate of up to 5 MS/s.