A 14bits 1GSPS Pipelined-SAR ADC with digital background calibration

Abstract

A 14bits 1GSps Pipelined-SAR (P-SAR) ADC design is presented in this paper. We apply 4 sub-stages with each stage using a 4-bit sub SAR ADC to reach an optimized overall performance. A new dynamic amplifier is proposed and used as the residue amplifier (RA), which improves the linearity and reduce the power largely. The multi-comparator structure is used in sub SAR ADC, which significantly reduces the comparator's reset time and hence increase the conversion speed a lot. For each single comparator, a two-stage structure is designed to effectively reduce the kickback noise. Besides, since it is extremely difficult to obtain precise interstage gain with open-loop dynamic amplifier, we propose a novel digital background calibration technique based on comparator metastability to compensate the interstage gain error and capacitor mismatches. This P-SAR ADC is designed in a 22nm FD-SOI process. The simulation results show that our ADC achieves an SNDR of 69dB and an SFDR of 85dB respectively with the input signal frequency of 100MHz at a sampling rate of 1GS/s. The core ADC consumes 109mW (excluding the reference generator).