12-bit ADC Research Articles

Open-Source Heterogeneous Constrained Edge-Computing Platform for Smart Grid Measurements

This article presents a low-cost, open-source, heterogeneous, resource-constrained hardware platform called “Parallella” as a measurement device for edge-computing applications research in smart grid. The unique hardware architecture of the Parallella provides a multitude of edge-computing resources in the form of a Zynq SoC (dual-core ARM + FPGA) and a 16-core co-processor called Epiphany. A multifunctional intelligent electronic device (IED) design is demonstrated to showcase the capabilities of the platform. A custom I/O board has been developed for the desktop and embedded versions of Parallella, which can be interfaced with external daughter boards and peripherals for measurements. One such daughter board is an analog sensing board, which can measure voltages of all the three phases and four line currents using a 16-bit synchronous ADC set at 32 kHz. The ADC samples are synchronized to the PPS time clock of a GPS unit for providing global time reference. These captured seven-channel raw waveform data are sent to a cloud server over a bandwidth-limited communication channel using a custom anomaly-aware data compression algorithm implemented on the ARM. A phasor measurement algorithm using the Teager energy operator (TEO) is implemented on the field-programmable gate array (FPGA). A parallel power quality (PQ) measurement algorithm is implemented on the Epiphany. The obtained measurements are found to be comparable to a commercial power analyzer.

Development of an Economical, Linear CCD Based Spectrometer

Spectrometry provides vital information about the composition of electromagnetic radiation by measuring wavelengths of light over a wide range of the electromagnetic spectrum. In this work, design and construction of an economical linear CCD spectrometer and a computer application is presented. A sample of the light source travelling through an optical fiber enters the device and the spectrum produced by a diffraction grating is projected on a linear CCD detector. The data is sampled using a 10-bit ADC to the microcontroller memory and finally transferred to the computer via a full speed USB connection. In the computer, the data is digitally processed and displayed through a graphical user interface with several useful functionalities. The device is sensitive to electromagnetic waves of wavelengths ranging from 400 to 800 nm, which is decided by the sensitivity of the silicon CCD detector. The device performs in par with commercially available handheld spectrometers and is equipped with wavelength and amplitude calibration capabilities.

Use of web services in technological process control systems

The optimal control of technological objects and processes is usually implemented by computer control systems with complicated structure and relations between elements. On the one hand, it allows to perform the functions of automatic control and regulation, alarms, process status registration and visualization. On the other hand, this leads to a significant complication of the systems because of increased process intensity, speed, accuracy and quality requirements.Use of web services is the most popular approach to solve the problem of integration and coordination of system elements. It is based on the exchange of messages of a special (universal) format between parts of the system and processing the responses.The role of web service and its place in control system has been analyzed. The most appropriate place is between the levels of PLC - controllers and SCADA one. It allows you to receive current information about the state of the technological process and implement the following functions: data acquisition by controllers; storage data to the database; providing data to the operator on demand and it’s visualization in real time; monitoring and alarms of process parameters.The web service build with Microsoft ASP.NET has been proposed for use in computer control systems. The key benefit of this technology are: open-source, cross-platform, fast and scalable. The development of web-services in control systems is a universal approach that can be applied to a large class of objects or processes. In the article the web service for temperature control has been proposed. The key task of the system is temperature data acquisition from the control object, to save information to the database, visualize the temperature curve, notify when the temperature exceeds limits.Since the Microsoft technology stack is already in use, MS SQL has been chosen. To increase the speed of development the Entity Framework Core application has been used, which provides a way to interact with data. To provide the security of the database and prevent development errors, a library has been implemented to access the database. It provides two interfaces Repository and Unit Of Work. Repository is an interface for interacting with each object in the database. The advantage of this interface is abstraction that removes dependency of a specific class implementation.The hardware of control system consists of programmable platform Arduino and such modules: Arduino Uno – the platform on the Atmega 328 microcontroller with built-in interface SPI, I2C, UART, 5 analog inputs and 13 discrete built-in power lines 3.3 and 5 V; MAX6675 - signal conversion module (12-bit ADC); thermocouple type K; ESP8266-01 - module with Wi-Fi interface; DS3132 - real time clock module.The modules interact according to the following algorithm: Arduino calls the thermocouple module and remembers the value, then calls the time module and forms a data period in which it places the time and temperature value. The controller module transmits data to the ESP8266-01 via a programmed UART interface. The Wi-Fi module reads data on the UART bus, forms HTTP request headers and sends JSON text to the server.Thus, web service for SCADA-level has been developed. The control object based on the Arduino hardware platform has been simulated. The developed web service provides the necessary level of security, high indicators of convenience of the human-machine interface, allows to analyze the object and track the past state of the system.

Digital Error Correction Logic for Pipelined ADC Using 1.5Bits/Stage

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

A Square Wave-Based Digital Foreground Calibration Algorithm of a Pipeline ADC Using Approximate Harmonic Sampling

This brief proposes a digital foreground calibration algorithm of a pipeline ADC, using the Square wave signal as the input. The principle of equivalent radix extraction technique using approximate harmonic sampling is used to remove the ADC non-linearities. Linearity errors caused due to finite op amp gain, capacitor mismatches and effect of parasitic capacitance are eliminated by the proposed calibration technique. Two front-end stages of a 12-bit pipeline ADC are incorporated with low amplifier gain of 40 dB, capacitor mismatch of ±5 % ≤ γ ≤ ±10 %. Non-linearities arising due to these factors are calibrated and results are verified using behavioural simulation.

A numerical simulation of a near-infrared three-channel trace ammonia detection system using hollow core photonic crystal fiber

A simulation model of the fiber-structure trace ammonia detection system based on near-infrared laser absorption spectroscopy is proposed. The distributed feed-back (DFB) diode laser modulation, photodetector, and signal processing are simulated by programming using matlab code while the noise amplitude selected to the sampling accuracy of commercial 12-bit ADC. The wavelength 1512 nm was selected to calculate the absorption coefficient of mixture containing ammonia, carbon dioxide, and water vapor. When the length of fiber-structure gas chamber was set to 10 cm, 1 m, and 10 m, respectively, ammonia with concentration from 0.2 ppm to 10,060 ppm can be detected. The dynamic range of this simulation have covered 5 orders of magnitude which never achieves in traditional detection system. Our work provides a potentially valuable option to establish the ammonia detection system of more portable, high sensitivity, and large detection range.

Research on mechanical vibration monitoring based on wireless sensor network and sparse Bayes

Mechanical vibration monitoring for rotating mechanical equipment can improve the safety and reliability of the equipment. The traditional wired monitoring technology faces problems such as high-frequency signal pickup and high-precision data collection. Therefore, this paper proposes optimization techniques for mechanical vibration monitoring and signal processing based on wireless sensor networks. First, the hardware design uses high-performance STM32 as the control center and Si4463 as the wireless transceiver core. The monitoring node uses a high-precision MEMS acceleration sensor with a 16-bit resolution ADC acquisition chip to achieve high-frequency, high-precision acquisition of vibration signals. Then, the bearing vibration signal optimization method is studied, and the sparse Bayes algorithm is proposed as a compressed sensing reconstruction algorithm. Finally, the difference in reconstruction accuracy between this method and the traditional reconstruction algorithm is compared through experiments and the effect of this method on the reconstruction performance is analyzed when different parameters are selected.

ADC Quantization Effects in Two-Loop Digital Current Controlled DC-DC Power Converters: Analysis and Design Guidelines

This paper analyzes the presence of undesired quantization-induced perturbations (QIP) in a dc-dc buck-boost converter using a two-loop digital current control. This work introduces design conditions regarding control laws gains and signal quantization to avoid the quantization effects due to the addition of the outer voltage loop in a digital current controlled converter. The two-loop controller is composed of a multisampled average current control (MACC) in the inner current-programmed loop and a proportional-integrator compensator at the external loop. QIP conditions have been evaluated through simulations and experiments using a digitally controlled pulse width modulation (DPWM) buck-boost converter. A 400 V 1.6 kW proof-of-concept converter has been used to illustrate the presence of QIP and verify the design conditions. The controller is programmed in a digital signal controller (DSC) TMS320F28377S with a DPWM with 8.96-bit equivalent resolution, a 12-bit ADC for current sampling, and a 12-bit ADC for voltage sampling or a 16-bit ADC for voltage error sampling.

A well-type NaI(Tl)/BC404 phoswich detector for atmospheric radioxenon monitoring

The monitoring of radioxenon in the atmosphere is one of several methods to detect nuclear weapon tests as part of the Comprehensive Nuclear Test Ban Treaty. For ultra-low radioxenon detection, a phoswich detector with two scintillators coupled to a single photomultiplier was explored to simplify the time-based coincidence detection systems such as SAUNA and ARSA. We present a well-type NaI(Tl)/BC404 phoswich detector, newly developed by the Institute of Nuclear Physics and Chemistry, which consist of a thin BC404 cell to detect beta and conversion electrons, and a NaI(Tl) crystal to detect X-rays and gamma-rays. Moreover, the pulses of the detector were sampled and processed at 1GS/s with 10-bit ADC by a high-speed digitizer. In the preliminary experiments with various sources, the detector was test to have comparable sensitivity with the existing detectors in energy resolution, detection efficiency, background, memory effect and MDCs. The gamma resolution achieved 6.9% at 662keV. The coincidence efficiency of 133Xe at 81keV region is about 71% while gas loss in the stainless tube and the valve was accounted. In addition, the MDC of 133Xe was calculated by 0.2mBq/m3 under current gas process capability.

SenseBack - An Implantable System for Bidirectional Neural Interfacing.

Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. To resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing device that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary \textit{ex-vivo} and \textit{in-vivo} preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with 20 V of compliance and up to 315 A of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals.

A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization

A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. As such, an effective mismatch calibration circuit can allow the DAC to be scaled down to a much lower <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">kT/C</i> noise limit, thereby increasing the overall ADC power efficiency. This paper reviews some of the most important reported mismatch calibration techniques and proposes a foreground calibration method based on a deterministic self-calibration and stochastic quantization. This approach is experimentally validated on a prototype 10-bit SAR ADC fabricated in TSMC 28-nm LP CMOS technology, demonstrating an INL and SFDR improvement of respectively 6.4 LSB and 14.9 dB at 85 MS/s.

Low Noise, Low Power 5-channel Sonar Signal Conditioning Receiver with 1.5 MS/s - 12.5 MS/s 16-bit Sigma-delta ADC for Ocean Acoustic Measurements

Low Noise, Low Power 5-channel Sonar Signal Conditioning Receiver with 1.5 MS/s - 12.5 MS/s 16-bit Sigma-delta ADC for Ocean Acoustic Measurements

A 10-bit SAR ADC using novel LSB-first successive approximation for reduced bitcycles

This paper presents a 10-bit ultra-low power least-significant bit first (LSB-first) successive approximation register analog-to-digital converter used in wearable electrocardiogram monitoring. Compared with the exsiting ones, the number of bitcycles taken in the proposed LSB-first scheme only relates to the difference between two adjacent samples and the capacitor array is reduced by 50%. Fabricated in 65 ​nm CMOS technology within a bio-sensor front-end circuit, the proposed LSB-first SAR ADC occupies an active area of 200 ​× ​450 ​μm2, consumes 60.8 ​nW ​at 10 ​kHz sampling rate, and achieves 58.4 ​dB SNDR.

Resolving soft X-ray absorption in energy, space and time in gaseous detectors using the VMM3a ASIC and the SRS

The implementation of the VMM3a Application-Specific Integrated Circuit (ASIC) into the Scalable Readout System (SRS) has opened a new domain for measurements with Micro-Pattern Gaseous Detectors (MPGDs). In the presented studies we demonstrate the capabilities of this system, specifically the time-resolution in the nanosecond regime in combination with a continuous multichannel readout and a 10-bit ADC. We can now resolve the interaction of argon fluorescence X-ray photons created in a gaseous detector and utilise these interactions to determine the electron drift velocity in our detector and to investigate the attenuation length of the fluorescence photons.

An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-Interleaved ADCs

Time-interleaving (TI) is a major trend for high-speed ADC designs. The major limitation of TI-ADC is the mismatches among ADC channels. Calibration techniques have been actively pursued to compensate the mismatches. In this paper, we present a new spectral calibration technique for TI-ADC. Although the technique does not run in the background, it does not need external calibration signals and has no constraint on the input signal, which is similar to blind estimation. Compared to benchmark designs, the new technique involves much less calibration hardware overhead, and calibrates all mismatches with much less time. In practice, this efficient technique can run repetitively to track the environment changes. It addresses the needs from practical TI-ADCs well. The technique is verified with extensive simulations on a 2GS/s 12-bit 16-channel ADC. With mismatch spurs over -40dBc, the technique can reliably suppress the spurs to be lower than -80dBc within about 4000 samples without the need of iteration.

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Nonvolatile computing-in-memory (nvCIM) exhibits high potential for neuromorphic computing involving massive parallel computations and for achieving high energy efficiency. nvCIM is especially suitable for deep neural networks, which are required to perform large amounts of matrix–vector multiplications. However, a comprehensive quantization algorithm has yet to be developed, which overcomes the hardware limitations of resistive random access memory (ReRAM)-based nvCIM, such as the number of I/O, word lines (WLs), and ADC outputs. In this article, we propose a quantization training method for compressing deep models. The method comprises three steps: input and weight quantization, ReRAM convolution (ReConv), and ADC quantization. ADC quantization optimizes the error sampling problem by using the Gumbel-softmax trick. Under a 4-bit ADC of nvCIM, the accuracy only decreases by 0.05% and 1.31% for the MNIST and CIFAR-10, respectively, compared with the corresponding accuracies obtained under an ideal ADC. The experimental results indicate that the proposed method is effective for compensating the hardware limitations of nvCIM macros.

Mitigate Parasitic Resistance in Resistive Crossbar-based Convolutional Neural Networks

Traditional computing hardware often encounters on-chip memory bottleneck on large-scale Convolution Neural Networks (CNN) applications. With its unique in-memory computing feature, resistive crossbar-based computing attracts researchers’ attention as a promising solution to the memory bottleneck issue in von Neumann architectures. However, the parasitic resistances in crossbar deviate its behavior from the ideal weighted summation operation. In large-scale implementations, the impact of parasitic resistances must be carefully considered and mitigated to ensure circuits’ functionality. In this work, we implemented and simulated CNNs on resistive crossbar circuits with consideration of parasitic resistances. Moreover, we carried out a new mapping scheme for high utilization of crossbar arrays on convolution, and a mitigation algorithm to mitigate parasitic resistances in CNN applications. The mitigation algorithm considers parasitic resistances as well as data/kernel patterns of each layer to minimize the computing error in crossbar-based convolutions of CNNs. We demonstrated the proposed methods with implementations of a 4-layer CNN on MNIST, and residual neural network (ResNet) (20, 32, and 56) on CIFAR-10. Simulation results show the proposed methods well mitigate the parasitic resistances in crossbars. With our methods, modern CNNs on crossbars can preserve ideal (software) level classification accuracy with 6-bit ADCs and DACs implementation.

A reliable bubble sorting calibration method for SAR ADC

This paper presents a calibration method based on capacitor-sorting and capacitor-reconfiguring techniques to improve the Signal-to-Noise-and-Distortion Ratio (SNDR)and Spurious Free Dynamic Range (SFDR) of the successive-approximation-register analog-to-digital converter (SAR ADC). This paper first proposes a circuit for comparing capacitors and currents. Then the circuit that performs bubble sorting of capacitors is realized. By using the calibration method proposed in this work, the mismatch of the capacitors has been greatly decreased, thereby improving the performance of the SAR ADC. The calibration method is verified by simulating a 1 Ms/s 14-bit SAR ADC in 0.18 μm technology, the simulation results show that the SFDR is enhanced by about 18 dB and the SNDR is enhanced by about 10 dB, finally, the Figure of Merit (FOM) achieves 26.24 fJ/conv-step.

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

Following new Trigger and Data AcQuisition (TDAQ) buffering and rate requirements as well as the high radiation doses and the pileup conditions of the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter electronics will be upgraded to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range. The triangular calorimeter signals are amplified and shaped by the analogue electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers to meet these requirements are ongoing in CMOS 130 nm. In order to digitize the analogue signals on two gains after shaping, radiation-hard, low-power 40 MHz 14-bit ADCs are developed using a SAR architecture in 65 nm CMOS. Characterization of the first prototypes of the Front-End components show good promise to fulfill all the requirements. The signals will be sent at 40 MHz to the off-detector electronics, that will make use of FPGAs connected through high-speed links to perform energy and time reconstruction through the application of digital filtering and appropriate corrections. Reduced data are sent with low latency to the first level trigger, while the full data are buffered until the reception of trigger accept signals. The data-processing, control and timing functions will be realized by dedicated boards connected through ATCA crates. Results of tests of the first prototypes of Front-End components will be presented, along with design studies on the performance of the off-detector readout system.

A CMOS two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique

This paper describes a two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique. The proposed 12-bit SAR ADC consists of two SAR ADCs connected in parallel, so that the sampling rate can be doubled. The first 12-bit SAR ADC is employed to determine the 12 bits and the second 12-bit SAR ADC utilizes the upper 6-bits of the first one, so that it can determine the lower 6-bits and save switching energy. The proposed two-way time interleaved 12-bit SAR ADC is implemented with a CMOS 180 nm 1-poly 6-metal process. The measurement results demonstrate ENOB of 10.2 bits, SNDR of 62.9 dB, power consumption of 69 μW, INL/DNL of ± 1.8 LSB, and Walden FoM of 5.9 fJ/step.