6T Static Random Access Memory Research Articles

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Low standby leakage 12T SRAM cell characterisation

ABSTRACTIn this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.

Low power and robust memory circuits with asymmetrical ground gating

Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24× and 2.39×, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52× and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight-transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells.

High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.

Design and analysis of single- ended robust low power 8T SRAM cell

This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.

4 × 4 Squared Memory Array with Compact, Efficient and Low Leakage 7T Static Random Access Memory Cell

4 × 4 Squared Memory Array with Compact, Efficient and Low Leakage 7T Static Random Access Memory Cell

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Although near-threshold ( $V_{\mathrm {\mathbf {th}}}$ ) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near- $V_{\mathrm {\mathbf {th}}}$ 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub- $V_{\mathrm {\mathbf {th}}}$ leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.

FinFET based 6T SRAM Cell for Nanoscaled Technologies

is a non planar modeling device for small size transistors (less than 45nm) will replace traditional planar MOSFETs because of superior ability to control short channel effects, off-state leakage current, power dissipation and propagation delay. Static random access memories (SRAMs) consume nearly 94% of chip area in most present system-on- chip (SoC) circuits. In this paper, a standard 6T SRAM cell has been designed using dual gate FinFET transistors and its performance for read/write operation is analyzed in terms of average power consumption, propagation delay, power delay product (PDP) and static noise margin (SNM) for nanoscaled technologies. A comprehensive comparison is carried out with conventional 6T CMOS SRAM cell for 45nm, 32nm and 16nm nanoscaled technologies. A reduction in power delay product by 87.5%, 88.8% and 99.1% in read operation and 90.4%, 89.2% and 96.9% in write operation of FinFET based SRAM cell at 45nm, 32nm and 16nm technology nodes respectively as compared to 6T CMOS SRAM cell. Also an improvement in static noise margin by 27.5%, 31.5% and 8.9% of FinFET based SRAM cell is obtained at 45nm, 32nm and 16nm technology nodes respectively.

A boostless write optimised single ended robust 7T SRAM cell for ultra-low power memory design

ABSTRACTA boostless 7T static random access memory SRAM cell with high writability, improved stability and reduced read failure is proposed. The proposed 7T utilises feedback cutting during write operation, which does not require a boosted supply for single access transistor. This technique enhances the writability of the SRAM cell at ultra-low voltage (ULV) supply without any write assist at 90 and 20 nm technology nodes. The proposed 7T SRAM cell has write trip point (WTP) at 85.25 mV, whereas 5T fails to write ‘1’. The mean to sigma ratio (µ/σ) is improved by a factor of 1.08× and 7.14× for hold static noise margin (HSNM) and read margin, respectively, as compared to standard 5T at 300 mV in UMC 90 nm process technology. This also saves 26.41% read and 22.72% write power as compared to 5T SRAM cell at 300 mV. Moreover 7T also shows an improvement of 2.91% in HSNM and 1.85% in read margin by using FinFET technology.

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09%, while providing similar read speed as compared with the conventional six-transistor (6T) SRAM cell in a 16-nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by $4.57\times $ and $3.90\times $ with the proposed 9-CN-MOSFET SRAM cell as compared with the conventional 6T SRAM cell and a previously published eight-transistor (8T) SRAM cell, respectively. A 1 Kibit SRAM array with the new memory cells consumes 34.18% and 12.27% lower leakage power as compared with the memory arrays with 6T and 8T SRAM cells, respectively, in idle mode. The overall electrical quality is enhanced by up to $13.63\times $ with the proposed 9-CN-MOSFET memory circuit as compared with the other memory cells that are evaluated in this paper.

Analysis of leakage current and power reduction techniques in FinFET based SRAM cell

In this paper we have proposed a FinFET based 6T static random access memory (SRAM) cell. FinFET devices can be used to improve the performance, reduce the leakage current and power dissipation. The purpose of this article is to reduce the leakage current and leakage power of FinFET based 6T SRAM cell using various techniques in 45 nm technology. FinFET based 6T SRAM cell has been designed and analysis has been carried out for leakage current and leakage power. For low power memory design the most important problem is to minimize the sub-threshold leakage current and gate leakage current. This work introduces a technique based on threshold voltage, gate oxide thickness and power supply setting together to minimize sub-threshold and gate leakage current of 6T SRAM cell. These simulation results are carried out using Cadence Virtuoso Tool at 45 nm technology.

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

A novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T writes "1" through one NMOS and writes "0" using two NMOS pass transistors. The 7T has mean $$(\mu )$$(μ) of 222.3 mV (74.1 % of supply voltage) for write trip point where 5T fails to write "1" at 300 mV. It gives mean $$(\mu )$$(μ) of 276 mV (92 % of supply voltage) for read margin, while 5T fails due to read disturb at 300 mV. The hold static noise margin of 7T is maintained close to that of 5T. The read operation of 7T is 22.5 % faster than 5T and saves 10.8 % read power consumption. It saves 36.9 % read and 50 % write power consumption as compared to conventional 6T. The novel design of proposed 7T consumes least read power and achieves the lowest standard deviation as compared to other reported SRAM cells. The power consumption of 1 kb 7T SRAM array during read and write operations is 0.70$$\times $$× and 0.65$$\times $$×, respectively, of 1 kb 6T array. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low-voltage supply without any write assist in UMC 90 nm technology node. Future applications of the proposed 7T cell can potentially be in low-voltage, ultra-low-voltage and medium-frequency operations like neural signal processor, sub-threshold processor, wide-operating-range IA-32 processor, FFT core and low-voltage cache operation.

Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance

One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , inhibits V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide-indium arsenide (GaSb-InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FIN</sub> , and ultrathin body thickness, T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> , variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on nand p-FinFETs shows higher 3σ(VT Lin) of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As bulk nand Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> , shows that HTFETs require 10T SRAM cell architecture and less than 4% variation in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> for their V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCmin</sub> to approach 200 mV.

A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

The minimum operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6σ from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.

Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells

The commonly used four metrics for write stability were measured and compared based on the same set of 2048 (2k) six-transistor (6T) static random access memory (SRAM) cells by the 65 nm bulk technology. The preferred one should be effective for yield estimation and help predict edge of stability. Results have demonstrated that all metrics share the same worst SRAM cell. On the other hand, compared to butterfly curve with non-normality and write N-curve where no cell state flip happens, bit-line and word-line margins have good normality as well as almost perfect correlation. As a result, both bit line method and word line method prove themselves preferred write stability metrics.

FinFET-based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect

In this paper, we have proposed a FinFET-based 6T Static Random Access Memory (SRAM) cell. The proposed FinFET-based 6T SRAM cell offers better stability in terms of Static Noise Margin (SNM) and Read Noise Margin (RNM). During the read operations, SRAM cell stability analysis is based on the SNM because many memory errors may occur. Since SNM changes with each cell operation, a complete analysis of SNM in read mode is required. In this paper, we have looked into the SRAM cell SNM during read mode analysing various options to improve cell stability. These techniques are based on the transistor width, word-line, bit-line and supply voltage modulations. We showed that it is possible to improve the stability of SRAM cell during read operations, while reducing word-line voltage which reduces the leakage current. We have also analysed the temperature effect on SNM, leakage current and leakage power for FinFET-based SRAM cell.