A boostless write optimised single ended robust 7T SRAM cell for ultra-low power memory design

Abstract

ABSTRACTA boostless 7T static random access memory SRAM cell with high writability, improved stability and reduced read failure is proposed. The proposed 7T utilises feedback cutting during write operation, which does not require a boosted supply for single access transistor. This technique enhances the writability of the SRAM cell at ultra-low voltage (ULV) supply without any write assist at 90 and 20 nm technology nodes. The proposed 7T SRAM cell has write trip point (WTP) at 85.25 mV, whereas 5T fails to write ‘1’. The mean to sigma ratio (µ/σ) is improved by a factor of 1.08× and 7.14× for hold static noise margin (HSNM) and read margin, respectively, as compared to standard 5T at 300 mV in UMC 90 nm process technology. This also saves 26.41% read and 22.72% write power as compared to 5T SRAM cell at 300 mV. Moreover 7T also shows an improvement of 2.91% in HSNM and 1.85% in read margin by using FinFET technology.