Low standby leakage 12T SRAM cell characterisation

Abstract

ABSTRACTIn this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.