6T Static Random Access Memory Research Articles

Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs

In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The active power is reduced by reducing the supply voltage when the memory is functional and the standby power is reduced by reducing the gate and sub-threshold leakage currents when the memory is idle. This paper explored an integrated approach at the architecture and circuit level to reduce the leakage power dissipation while maintaining high performance in deep-submicron cache memories. The proposed memory bit-cell makes use of the pMOS pass transistors to lower the gate leakage currents while full-supply body-biasing scheme is used to reduce the sub-threshold leakage currents. To further reduce the leakage current, the stacking effect is used by switching off the stack transistors when the memory is ideal. In comparison to the conventional 6T SRAM bit-cell, the total leakage power is reduced by 50% while the cell is storing data ‘1’ and 46% when data ‘0’ at a very small area penalty. The total active power reduction is achieved by 89% when cell is storing data 0 or 1. The design simulation work was performed on the deep-sub-micron CMOS technology, the 45nm, at 250C with VDD of 0.7V.

Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect Transistor

In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field-effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (Hfin)/fin width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation results are experimentally validated. The multi-fin FinFET (AR = 2) has better channel controllability than the multifin trigate (AR = 1) and multi-fin quasi-planar (AR = 0.5) FETs. A six-transistor (6T) static random access memory (SRAM) using multi-fin FinFETs also provides the largest static noise margin because it supports the highest transconductance in FinFETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multi-fin transistors are further examined, and compared with those of an inverter with single-fin transistors. The multi-fin inverter has a shorter delay because it is dominated by the driving current of the transistor. With respect to random-dopant-induced fluctuations, the multifin FinFET suppresses not only the surface potential but also its variation because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants on the circuits are attenuated. The results of this study provide insight into the DC, and circuit characteristics of multifin transistors and associated random dopant fluctuations.

Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

In this study, a three-dimensional “atomistic” coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM ( σ SNM) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the σ SNM is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era.

A 500-MHz DDR High-Performance 72-Mb 3-D SRAM Fabricated With Laser-Induced Epitaxial c-Si Growth Technology for a Stand-Alone and Embedded Memory Application

For the first time, the smallest 3-D stacked six-transistor (6T) static-random-access-memory (SRAM) cell technology is successfully developed by using a laser crystallization process to grow perfect single-crystal Si layers on the amorphous dielectric Si dioxide layers. The SRAM cell size is 36 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.36 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 100-nm complementary MOS technology. The 3-D SRAM cell consists of three differently layered and 3-D stacked-cell thin-film transistors (TFTs), whose channel area is a perfect single-crystal Si. The electrical characteristics of the pass n-channel MOS TFT and the load p-channel MOS TFT are very close to those of the planar bulk transistors because their channel Si layers are perfect single-crystal films. A 500-MHz high-performance and highly cost effective 72-Mb-density 3-D SRAM, which is comparable to the conventional planar 6T SRAM in electrical performance, was successfully fabricated for a stand-alone and embedded memory, with this 3-D stacked 6T SRAM cell technology, the low-temperature TFT formation process, periphery-only Co salicidation, and the W shunt wordline scheme.

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

A design for the polycrystalline gate is developed for low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The asymmetry characteristics of the device are also improved by the poly deposition. The of the cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well asymmetry.

A Low Power SRAM Cell with High Read Stability

In this paper, a 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is proposed. In conventional six transistor (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Existing 9T SRAM cell design increases the read static noise margin (SNM) by twice as compared to conventional 6T SRAM cell by completely isolating the bit-lines during the read operation. But the write operation is performed in this cell, by charging/discharging of large bit line capacitances causing 22.5% increase in dynamic power consumption. In the proposed technique, the SRAM cell utilizes charging/discharging of a single bit-line (BL) during write operation, resulting in reduction of dynamic power consumption by 45% as compared to a conventional 6T SRAM cell while the read SNM is also maintained at twice the read SNM of the conventional 6T SRAM cell. All simulations of the proposed 9T SRAM cellhas been carried out in 0.13 ¹m CMOS technology.

A proposed SRAM cell for low power consumption during write operation

PurposeLow power static‐random access memories (SRAM) has become a critical component in modern VLSI systems. In cells, the bit‐lines are the most power consuming components because of larger power dissipation in driving long bit‐line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit‐line. The aim of the paper is to propose a new SRAM cell architecture to reduce the power consumption during write 0 and write 1 operation.Design/methodology/approachThe proposed circuit includes two tail transistors in the pull‐down path of inv‐A and inv‐B. The simulated results of the proposed cell is compared with Conventional 6T SRAM cell and zero‐asymmetric SRAM cell.FindingsThe proposed SRAM cell consumes less power than the conventional SRAM cell during write operation. The write access delay is reported to be lower than conventional and ZA SRAMs in the proposed circuit. The read operation is similar to Conventional SRAM cell but due to tail transistors the read access delay and stability is poor in the present circuit which can be improved by careful transistors sizing.Originality/valueThe paper proposes a SRAM cell to reduce the power in write “0” as well as write “1”operation by introducing two tail transistors.

A New Single-Ended SRAM Cell With Write-Assist

A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a one through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active power and leakage power can be significantly reduced. Leakage charge can be pooled to help precharge bit lines. Cell area and performance are competitive with traditional SRAM cell area and performance

The ITFET: A Novel FinFET-Based Hybrid Device

A novel nanoscale hybrid device (the ITFET) comprising a double-gate (DG) FinFET and a single-gate silicon-on-insulator (SOI) MOSFET, with a common gate, is defined and assessed using a process/physics-based compact model [University of Florida DG model (UFDG)] and 3-D numerical simulations. Significantly higher, and variable, on-state current per pitch, relative to the current of the FinFET, can be achieved with a properly designed ITFET, with the off-state current being governed by the body thickness of the (fully depleted) SOI device. The ITFET can be especially advantageous in FinFET circuits that require device ratioing, such as the 6T-static random access memory (SRAM) cell. Outstanding UFDG/Spice3-predicted characteristics of the FinFET-based SRAM cell, with ITFETs used for the pull-down transistors without any area penalty, are presented