14nm FinFET Research Articles

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

This paper proposes a bitline charge sharing suppressed bitline read assist (BCS RA) and a cell supply collapse write assist (BCS WA). The proposed BCS RA suppresses the bitline (BL) voltage to half of the supply voltage ( $\text{V}_{\mathrm {DD}}$ ) using the charge sharing BL precharger for improving read stability and energy efficiency. In the proposed BCS WA, the charge on cell $\text{V}_{\mathrm {DD}}$ (CV $_{\mathrm {DD}}$ ) is shared with that on the BL precharged to half- $\text{V}_{\mathrm {DD}}$ by the charge sharing write driver, which causes the collapse in CVDD. In cells with poor writability, CVDD can be collapsed more by the self-collapse paths when the write operation is performed. Thus, the BCS WA improves writability and reduces write energy consumption. The simulation results using 22-nm FinFET technology show that static random access memory (SRAM) using BCS RA and WA consumes much less read and write energy than SRAMs using state-of-the-art assists while achieving a comparable minimum operating $\text{V}_{\mathrm {DD}}$ to SRAMs using state-of-the-art assists. Even compared to the SRAM without assists, the read and write energy consumption is reduced by 31% and 26%, respectively.

A 1S Direct-Battery-Attach Buck Voltage Regulator With 5-Stack Thin-Gate 22-nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers

A 1S Direct-Battery-Attach Buck Voltage Regulator With 5-Stack Thin-Gate 22-nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers

High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops

Recently, nonvolatile systems with nonvolatile flip-flops (NVFFs) have gained prominence for their energy efficiency in energy-harvesting devices and battery-operated Internet of Things applications. They are normally-off instantly-on, and thus, can save energy effectively owing to their zero standby power consumption. An NVFF stores the computing state in nonvolatile memories (NVMs) when the power is off. A ferroelectric field-effect transistor (FeFET) is one of the most promising NVMs owing to its high $\text{I}_{\mathrm {on}}/\text{I}_{\mathrm {off}}$ ratio and low write power. Three FeFET-based NVFFs (previous FeFET-out NVFF-1/-2 and FeFET-in NVFF) were recently proposed to improve the area, power, and speed; however, they still have their own problems. Previous FeFET-out NVFF-1 has large area overhead and previous FeFET-out NVFF-2 does not properly perform restore operation. Previous FeFET-in NVFF has a long clock-to-Q delay and high operating energy. This paper introduces two novel FeFET-based NVFFs (proposed FeFET-out and -in NVFFs). Proposed FeFET-out NVFF reduces the large area overhead of previous FeFET-out NVFF-1 and corrects the malfunction in the restore operation of previous FeFET-out NVFF-2. Proposed FeFET-in NVFF achieves a better clock-to-Q delay, operating energy, and area than the previous FeFET-in NVFF. Monte Carlo simulations based on an industry-compatible 10-nm FinFET model are performed for a comparative analysis. Proposed FeFET-out NVFF achieves 17.6% smaller area with slightly higher (6.3%) operating energy and only 0.8% slower clock-to-Q delay than previous FeFET-out NVFF-1. Proposed FeFET-in NVFF achieves 18.9% shorter clock-to-Q and 3.0% smaller operating energy with 8.7% smaller area than the previous FeFET-in NVFF.

Compact Single-Phase-Search Multistate Content-Addressable Memory Design Using One FeFET/Cell

Content-addressable memories (CAMs) are widely used for data-centric applications where one must search for data patterns. CMOS CAMs can incur large areas and, hence, power consumption. Nonvolatile (NV) devices, such as ferroelectric field-effect transistors (FeFETs) and resistive random access memories, have been used in the design of NV CAMs to improve both logic density and power consumption. To further improve logic density, this article proposes a compact, multistate CAM (MCAM) that can store 3 bits in a cell using just one FeFET and three FinFETs per cell. Moreover, the proposed MCAM does not require a precharging phase for search as is typical with other CAM designs, which can lead to improved performance. Simulations with experimentally calibrated 22-nm FeFET and 22-nm FinFET technology models suggest that the proposed 3T1Fe-MCAM can perform up to 7.1× faster search operations with up to 28.8× lower area-energy-delay product compared with state-of-the-art ternary/analog CAM designs. To show that the proposed MCAM array can accurately detect all worst case matches/mismatches, we design an MCAM array with 11 cells per row (to represent a 32bit number). We also study how the nonidealities related to programming/search voltages impact performance metrics and show that the proposed MCAM can tolerate up to 15-mV noise during programming and up to 20-mV noise on search voltages even in a worst case match/mismatch.

NPU Thermal Management

Neural processing units (NPUs) are becoming an integral part in all modern computing systems due to their substantial role in accelerating neural networks (NNs). The significant improvements in cost-energy-performance stem from the massive array of multiply accumulate (MAC) units that remarkably boosts the throughput of NN inference. In this work, we are the first to investigate the thermal challenges that NPUs bring, revealing how MAC arrays, which form the heart of any NPU, impose serious thermal bottlenecks to on-chip systems due to their excessive power densities. For the first time, we explore: 1) the effectiveness of precision scaling and frequency scaling (FS) in temperature reductions and 2) how advanced on-chip cooling using superlattice thin-film thermoelectric (TE) open doors for new tradeoffs between temperature, throughput, cooling cost, and inference accuracy in NPU chips. Our work unveils that hybrid thermal management , which composes different means to reduce the NPU temperature, is a key. To achieve that, we propose and implement PFS-TE technique that couples precision and FS together with superlattice TE cooling for effective NPU thermal management. Using commercial signoff tools, we obtain accurate power and timing analysis of MAC arrays after a full-chip design is performed based on 14-nm Intel FinFET technology. Then, multiphysics simulations using finite-element methods are carried out for accurate heat simulations in the presence and absence of on-chip cooling. Afterward, comprehensive design-space exploration is presented to demonstrate the Pareto frontier and the existing tradeoffs between temperature reductions, power overheads due to cooling, throughput, and inference accuracy. Using a wide range of NNs trained for image classification, experimental results demonstrate that our novel NPU thermal management increases the inference efficiency (TOPS/Joule) by $1.33\times $ , $1.87\times $ , and $2\times $ under different temperature constraints; 105 °C, 85 °C, and 70 °C, respectively, while the average accuracy drops merely from 89.0% to 85.5%.

Power Side-Channel Attacks in Negative Capacitance Transistor

Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Impact of Gamma-Ray Radiation on DC and RF Performance of 10-nm Bulk N-Channel FinFETs

In this article, the impact of gamma-ray radiation on DC and RF response of 10-nm bulk n-channel FinFETs is investigated. Firstly, the radiation tolerance of these devices under DC measurement conditions is reported as various layout level device parameters, such as the gate length ( $L_{G}$ ), number of fins ( $N_{FIN}$ ), and number of fingers ( $N_{FINGER}$ ) are scaled. Then for the first time, the impact of gamma-ray radiation on small-signal RF response of the 10-nm bulk FinFETs is reported, which includes some of the RF figures-of-merit (FOM), such as, the input transconductance, intrinsic current gain, intrinsic voltage gain, and unilateral power gain. Furthermore, the effect of device geometry scaling on maximum oscillation frequency, $f_{MAX}$ , degradation due to gamma-ray radiation is reported. DC results show that long channel devices with small $N_{FIN}$ and large $N_{FINGER}$ are least impacted by gamma-ray radiation as opposed to short channel devices with large $N_{FIN}$ and small $N_{FINGER}$ . The RF results show that gamma-ray radiation causes major degradation (~ 40%) in $f_{MAX}$ , while the cut-off frequency, $f_{T}$ remains mostly unchanged. Finally, an empirical model is developed to predict the degradation in $f_{MAX}$ with changing device geometries and gamma-ray radiation dose.

Comparative Analysis of Hot Carrier Degradation (HCD) in 10-nm Node nMOS/pMOS FinFET Devices

In 10-nm node core FinFETs, we analyzed the cause of higher hot carrier degradation (HCD) in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain materials, which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle (MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the pure HCD mechanisms to occur more in pFinFETs, which has higher temperature than nFinFETs. However, in pFinFETs, unlike nFinFETs, interface traps can be generated due to negative-bias temperature instability (NBTI) that occurs by the reaction between inversion holes and electrons of Si-H bonds. Also, since NBTI deteriorates more as the temperature increases, the phenomenon of higher degradation in pFinFET than nFinFET can be explained with the NBTI mechanism. Therefore, we propose an additional NBTI mechanism that is caused by high device temperature in pFinFETs even in the HCD condition. In addition, the main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that NBTI is dominant in pFinFETs. Finally, NBTI that can occur in the HCD condition was predicted through technology computer-aided design (TCAD) simulation. As a result, degradation due to pure hot carriers without NBTI occurs more in nFinFETs than in pFinFETs.

Improved Air Spacer for Highly Scaled CMOS Technology

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance ( ${C}_{{\text {eff}}}{)}$ . Such a ${C}_{{\text {eff}}}$ reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM

Cross-point-array nonvolatile ternary content-addressable memory (CPA nvTCAM) has recently emerged as an alternative to static random-access-memory-type TCAM, based on increased demands for high-capacity and low-power attributes. The CPA structure has various structural weaknesses such as the searchline (SL) combining with the dischargeline and the minimum line pitch of the matchline (ML). This study analyzes these weaknesses in detail for the first time and resolves the issues caused by these weaknesses using the proposed novel ML shield scheduling method with a matching probability-based flexible searching time technique (MLSS + MPFST). The proposed MLSS + MPFST resolves various issues and achieves greater than sixfold smaller cell size (8F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) than the non-CPA nvTCAM with the smallest cell size. To verify the proposed schemes, the Monte Carlo HSPICE simulations were performed using a 22-nm industry-compatible bulk FinFET model parameter in 20-nm resistive memory technology at a circuit level, and the gem5 simulations were performed at a system level. The simulation results indicated that the CPA nvTCAM with the proposed MLSS + MPFST achieved a comparable search operation time of 1 ns and a slight power consumption overhead of 10% but an acceptable system performance overhead of less than 0.6% by resolving the various issues, compared with the non-CPA nvTCAM having the best performance.

A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving sampling time and bandwidth mismatch. Above 10 GS/s, the THA is programmed to use two ping-ponged, or an optional (2 + 1) randomized, sample networks to spread the residual post-calibration interleaving spurs in the noise floor. The THA enables an input bandwidth of 18 GHz and employs dither injection and optional pseudorandom chopping. In the pipeline stages, dither-based background calibration detects and corrects gain, settling, memory, and kick-back errors. New dither-based background calibration algorithms are employed to detect and correct the arbitrary non-linearity in the form of integral non-linearity (INL) breaks and harmonic distortion up to the fifth order in the THA and in the references, DACs, and inter-stage open-loop amplifiers of the pipeline ADCs. Moreover, new dither-based background calibration is implemented to detect and correct the chopping non-idealities, memory errors, interleaving mismatches, and order-dependent randomization errors. Compared to the fastest state-of-the-art with similar performance, this ADC achieves 80% higher sample rate and 2.4× higher input bandwidth, and incorporates a THA that supports a 3.3× higher non-interleaved sample rate.

A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS

This article describes a synthesized fractional-N multiplying delay-locked loop (MDLL) implemented in Intel 22-nm FFL FinFET technology. A 2-bit time-period comparator (TPC) is proposed to adjust the ring oscillator frequency to suppress the spurs without introducing errors due to its inherent phase offset. A programmable delay is used to compare the periods of the MDLL output in time domain, reducing power consumption and making the design synthesizable. TPC 2-bit output achieves fast and robust locking without any initial calibration. The fractional multiplication ratio is achieved by using a digital-to-time converter (DTC) in the reference path with a replica of the digitally controlled oscillator (DCO) to automatically achieve a range of one DCO period. Any variation in DTC delay due to gain mismatch is corrected by a digital loop operating in the background. A detailed analysis of the small-signal model and noise of the proposed MDLL has also been presented. The core area of the synthesized design is 0.0052 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while operating over the frequency range from 1.2 to 3.8 GHz. The integrated rms jitter is 2.74 ps, and the spurs are below -47 dBc measured at 3.6175 GHz. Fractional-N MDLL power consumption is 3.19 mW with the figure of merit (FOM) of -226.3 dB.

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson's current mirror-based LS (WCMLS), CMLS-LED offers an enhanced speed by avoiding the threshold voltage drop of the feedback pFET and is free from the stability issue due to an incomplete output swing. Measurement results obtained from the test chip fabricated with 14-nm finFET technology, in which CMLS-LED is implemented with WCMLS, CPLS, and Osaki's LS, shows that the proposed CMLS-LED can widen the operating voltage range by 200 mV compared wth the CPLS, along with a speed improvement of 80%, when compared to WCMLS.

Performance Evaluation of 10nm SMG FinFET with Architectural Variation towards DC/RF and Temperature Aspects

FinFET structures of 10 nm technology node with promising design enhancements like hybrid spacer, raised source and drain extensions, and silicide interfaces have been analysed and compared. Analog figures of merit like drain current, transconductance, intrinsic gain, and transconductance generation factor are determined here. Furthermore, RF figures of merit like cut-off frequency, intrinsic delay, and gate capacitance are analysed. These parameters have been determined at three different temperatures (200 K, 300 K, 400 K) to study the effect of temperature on device performance.

Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a $2.2\times $ improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).

A Simulation Study on Minimizing Threshold Voltage Variability by Optimizing Oxygen Vacancy Concentration Under Metal Gate Granularity

In this work, we discuss the mitigation of threshold voltage ( ${V}_{{TH}}$ ) variability in nanoscale FinFET by exploiting the interaction of oxygen vacancies (OV) against metal gate granularity (MGG). Deposition of a metal gate on high- $\kappa $ dielectric HfO2 is known to generate OV in the dielectric which induces variability in surface potential. A higher workfunction of metal grain increases the probability of OV formation. Interestingly, while a higher workfunction metal grain decreases the surface potential of the channel underneath, the positive charge of OV increases the potential. Therefore, the concentration of OV can be controlled to negate the surface potential variability induced by MGG. We discuss the law of mass action-based concentration models of OV under MGG to analyze this. We also present TCAD simulations supporting the above hypothesis. In our simulations, for 10-nm channel FinFET, MGG-induced $\sigma $ ( ${V}_{{TH}}$ ) can be reduced to ~20 mV from ~35 mV for four-sided planar grains with 8 nm average edge length under the optimal OV concentration.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with a limited DCO tuning range of only 7.3–8.7 GHz (±8.7%). Phase modulation of narrowband signals (e.g., one resource block) using DTC could result in spurs in output spectrum due to the almost periodic nature of DTC errors. A theoretical analysis is presented that predicts the location of these spurs and a technique to eliminate such spurs by appropriately adjusting the PLL frequency is introduced. A new digitally controlled-edge-interpolator architecture is also presented to minimize dynamic errors, which is necessary in order to meet stringent cellular noise requirements. The DTC was implemented using digital synthesis and auto-place-and-route (APR) tools, requiring very limited analog layout resources. The TX was fabricated in 14-nm FinFET and it achieved a noise of −153/−150 dBc/Hz for LTE5/LTE20 in Band1 at +4-dBm output power with DTC power dissipation of 27 mW.

Defect-Oriented Test: Effectiveness in High Volume Manufacturing

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.