Abstract
This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.
Highlights
I N THE past, many papers have been published on stuck at (SA), transition delay faults (TDFs), gateexhaustive (GE) and timing-aware (TA) fault models
We have shown with test system results from a 14-nm FinFET chip that cell-aware test (CAT) patterns detect a huge amount of 4300 defective parts per million (DPPM) which are otherwise not detected with traditional SA, TDF, and all functional production test patterns
A very clear Vmin strength improvement was achieved from timing-aware CAT (TA-CAT) patterns versus TDF patterns and resulted in a reduction of 300 DPPM on top of reductions achieved by CAT patterns and all other production tests
Summary
I N THE past, many papers have been published on stuck at (SA), transition delay faults (TDFs), gateexhaustive (GE) and timing-aware (TA) fault models. To achieve a high outgoing product quality in general and zero DPPM especially for automotive products, it is essential to target physical defects explicitly, and as such a DOT method is required. This article gives a complete overview and detailed information about the DOT method, including details about physical defects, the generation of the needed test views, and the generation of DOT patterns. We present fault coverage measurements based on detected total critical area (TCA), and we provide guidance for achieving the highest product quality with lowest test costs.
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