Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach

Abstract

System level tests (SLTs) are important and expensive procedures to ensure high quality of IC products. In the volume production stage with stable yield, efforts such as random sampling have been made to improve testing efficiency. However random sampling doesn’t fully utilize information gathered before SLT and is not optimal. In this paper we propose both supervised (SVM) and unsupervised (AutoEncoder ) machine learning algorithms to predict or estimate the SLT failure based on earlier stage Final Test (FT) data and use the estimated pseudo probabilities to guide the selection of some chips for system level test. Experiments on a real product dataset, consisting of 158 wafers from 8 lots, each with 3118 FT testing variables reveal robustness of the models to data shift such as lot variations and missing test items. Through the gains chart of the models, we provide a flexible smart sampling strategy and demonstrate its potential of reducing SLT testing cost by 40% with minor impact on Defective Parts Per Million (DPPM). Our cases also show that such robust machine learning based sampling approach is very well suited for engaging adaptive test flow optimization to achieve balanced goals of improving test efficiency, reducing cost and ensuring high product quality at the same time.