Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

Abstract

In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.