6T Static Random Access Memory Research Articles

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications

ABSTRACT Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs.

Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell

The increasing demand of portable gadgets for emerging VLSI applications call for the low power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell has been designed using Negative Capacitance Junctionless FinFET (NC-JL FinFET) device. Further, the NC-JL FinFET based 6 T SRAM cell is evaluated for its power, stability and delay performance for read, write, and hold states and compared with conventional JL FinFET and published JL FinFET based SRAM. To investigate the reliability, the impact of ferroelectric thickness (TFE) and supply voltage (VDD) on the performance of NC-JL FinFET SRAM has also been investigated. It is shown that NC-JL FinFET SRAM dissipates 20% and ∼33% less static and dynamic power, with 1.2-, 1.5- and 1.18-times enhanced static noise margins in read, write, and hold state, respectively than JL FinFET SRAM. It also provides 37% and 20% faster read and write operations.

The Effects of Total Ionizing Dose on the SEU Cross-Section of SOI SRAMs

The total ionizing dose (TID) effects on single-event upset (SEU) hardness are investigated for two silicon-on-insulator (SOI) static random access memories (SRAMs) with different layout structures in this paper. The contrary changing trends of TID on SEU sensitivity for 6T and 7T SOI SRAMs are observed in our experiment. After 800 krad(Si) irradiation, the SEU cross-sections of 6T SRAMs increases by 15%, while 7T SRAMs decreases by 60%. Experimental results show that the SEU cross-sections are not only affected by TID irradiation, but also strongly correlate with the layout structure of the memory cells. Theoretical analysis shows that the decrease of SEU cross-section of 7T SRAM is caused by a raised OFF-state equivalent resistance of the delay transistor N5 after TID exposure, which is because the radiation-induced charges are trapped in the shallow trench, and isolation oxide (STI) and buried oxide (BOX) enhance the carrier scattering rate of delay transistor N5.

Reliability improved dual driven feedback 10T SRAM bit cell

This paper presents a dual driven feedback 10T (DDFB10T) static random-access memory (SRAM) bit cell with good read and write stability and that is free from half select issue. This DDFB10T cell working at VDD = 0.9 V achieves 1.5× higher static voltage noise margin (SVNM), and 0.48× lesser write trip voltage (WTV) than 6T SRAM cell. Monte Carlo simulation employing local and global variation using Cadence Virtuoso tool with 45 nm technology proves that the proposed bit cell is highly immune against process, voltage, and temperature (PVT) variations. The proposed DDFB10T bit cell exhibits lesser SVNM variability when it is normalized to that of 6T SRAM bit cell. The proposed DDFB10T cell is designed with the capability to provide a bit interleaved architecture for reducing half select issues.

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.

A 7T SECURITY ORIENTED SRAM BITCELL USING VLSI

Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor (6T) static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel power analysis attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000× lower write energy standard deviation between write ‘1’ and ‘0’ operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other power analysis resistant SRAM cells. Key Words: Power Analysis, SRAM Design, 6T SRAM, 7T SRAM, Power Dissipation Software Tools:  Tanner eda Tool

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

A Comparative Performance Analysis of 6T &amp; 9T SRAM Integrated Circuits: SOI vs. Bulk

This letter evaluates the performance of 6T &#x0026; 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed &#x0026; simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current &#x0026; voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD &#x0026; LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.

Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology

A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing

Frequent to-and-from data transfers in the von Neumann architecture limit the overall throughput. One of the promising approaches used to overcome von Neumann bottleneck is in-memory computing (IMC) that aims to embed computing in memory to reduce the transfer of memory-processor data. This study proposes a configurable 6-transistor (6T) static random access memory (SRAM) array with a multilevel shared structure for IMC. A multilevel shared structure can effectively improve the utilization rate of the module. In addition to the conventional SRAM operation, the configurable structure can also perform the sum of absolute differences (SAD) and Hamming distance (HD) calculations. To quickly identify the minimum value among multiple calculation results, a four-input sense amplifier (SA) is proposed. The performance of the proposed memory is simulated in a 65-nm CMOS process. The post-layout simulation results show good linearity of the multirow read in the SAD and HD modes. The mean time required by the four-input SA to obtain the result is 190 ps. The SAD and HD calculations yield consumptions of 67.44 fJ/byte and 0.64 fJ/bit, respectively, at 0.8 V. Furthermore, a single column-sharing comparator consumes 2.78 and 3.41 pJ at 0.8 V in the SAD and HD modes, respectively.

MONETA: A Processing-In-Memory-Based Hardware Platform for the Hybrid Convolutional Spiking Neural Network With Online Learning.

We present a processing-in-memory (PIM)-based hardware platform, referred to as MONETA, for on-chip acceleration of inference and learning in hybrid convolutional spiking neural network. MONETAuses 8T static random-access memory (SRAM)-based PIM cores for vector matrix multiplication (VMM) augmented with spike-time-dependent-plasticity (STDP) based weight update. The spiking neural network (SNN)-focused data flow is presented to minimize data movement in MONETAwhile ensuring learning accuracy. MONETAsupports on-line and on-chip training on PIM architecture. The STDP-trained convolutional neural network within SNN (ConvSNN) with the proposed data flow, 4-bit input precision, and 8-bit weight precision shows only 1.63% lower accuracy in CIFAR-10 compared to the STDP accuracy implemented by the software. Further, the proposed architecture is used to accelerate a hybrid SNN architecture that couples off-chip supervised (back propagation through time) and on-chip unsupervised (STDP) training. We also evaluate the hybrid network architecture with the proposed data flow. The accuracy of this hybrid network is 10.84% higher than STDP trained accuracy result and 1.4% higher compared to the backpropagated training-based ConvSNN result with the CIFAR-10 dataset. Physical design of MONETAin 65 nm complementary metal-oxide-semiconductor (CMOS) shows 18.69 tera operation per second (TOPS)/W, 7.25 TOPS/W and 10.41 TOPS/W power efficiencies for the inference mode, learning mode, and hybrid learning mode, respectively.

Analyzing the Effect of Uncertainty in Low Power SRAM Cells Using Artificial Intelligence Technique

This paper addresses the uncertainty that is present in the design of static random access memory (SRAM) cells using an artificial intelligence (AI) technique. The SRAM has much uncertainty in high-performance portable very large-scale integration (VLSI) chips due to their performance and storage density. This paper presents the way for solving the uncertainty problem by evaluating point-by-point recreation derived for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture for autonomous vehicles using AI algorithm. The adiabatic low power technique is implemented to enrich the configuration of the 6T-SRAM cells. The procedure of the adiabatic process will provide high loss in terms of dissipation of energy which is connected to ground (0V) and transition can be converted from ‘1’ to ‘0’. Moreover, this transition will be decreased to a high amount of degree within corresponding memory cells. Thus uncertainties with the AI model can able to deliver low power reduction using the automatic model of operation as standard adiabatic 6T SRAM cells are implemented. To prove the effectiveness in the reduction of uncertainties a low power margin is obtained with marginal values of 0.25 Volts which is much lesser than the existing models.

A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected Transistors

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.

Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells

The current generation aims for Low power electronic gadgets like cell phones, PDAs, etc. This urged demand is met through adopting low power reduction techniques. These gadgets also demand the presence of cache memories, which are fabricated via Static Random Access Memory (SRAM) Cells. Now the challenge is in designing low leakage SRAM cells by adopting power reduction techniques. The proposed work of 7T based Volatile and Non-Volatile SRAM cell is carried through adopting efficient low power reduction technique referred to as Improved Self Controllable Voltage Level (I-SVL). Proposed 7T SRAM cell is based on Improved Self Controllable Voltage Level (I-SVL) technique which controls the supply voltage in Idle and Non Idle mode of SRAM cell. Also Upper-ISVL and Lower-ISVL supplies the Vdd and Vss as per the requirement there by controlling the leakage power. The proposed I-SVL based 7T Volatile and Non-Volatile is designed and simulated using Cadence Virtuoso spectre tool by using CMOS technology with gpdk 45nm. Proposed work carried is efficient in terms of sub threshold and total leakage currents in comparison with the earlier work. The obtained sub threshold and total leakage current of the proposed volatile 7T SRAM cell based on the I-SVL shows improvements in lower values with existing work by 15% and 32%. Also proposed Non-volatile based I-SVL 7T SRAM cell resulted in lesser sub threshold and total leakage current by an amount of 97% and 93% in comparison with the earlier work. The gate leakage current of proposed Non-volatile 7T SRAM cell resulted in 57% lower value in comparison with the earlier work.

Half‐selection disturbance free 8T low leakage SRAM cell

SummaryThis work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.

Design of Low Power Transmission Gate Based 9T SRAM Cell

Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.