14nm FinFET Technology Research Articles

A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET

A 16-GS/s single 1.2-V supply direct RF-sampling capacitive D/A converter for soft radio base-station applications is implemented in a 16-nm FinFET technology. Due to co-integration with a wideband on-chip matching network, the D/A converter (DAC) is capable of signal synthesis between 600 MHz and 8 GHz, with a measured peak RF output power of +5.6 dBm. The linearity required by cellular base-station applications is achieved by employing several analog-domain linearization techniques, yielding a two-tone intermodulation distortion of better than −70 dBc up to the first Nyquist frequency. When transmitting a true multiband signal covering an instantaneous bandwidth of 1 GHz, an adjacent channel leakage ratio (ACLR) of better than −69 dBc is achieved. Digital segment mismatch correction is shown to improve the linearity of a segmented DAC in deep digital backoff operation. A full-rate digital pre-distortion (DPD) method with efficient model identification is experimentally demonstrated. Using DPD, the design achieves an spurious free dynamic range (SFDR) of better than 72 dBc over the entire 0.6–6-GHz frequency range.

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal–oxide semiconductor (NMOS) transistor or P-channel metal–oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal–oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power dissipation of 0.85W.

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor's scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop's sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

Investigating Heavy-Ion Effects on 14-nm Process FinFETs: Displacement Damage Versus Total Ionizing Dose

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no “rebound” in the ON-state current back to its initial high value; however, the OFF-state current “rebound” was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects.

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation-hardened variants present superior resiliency when either local or global triple modular redundancy (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

Implementation of UART Design for RF Modules Using Different FPGA Technologies

This paper is focused on the designing of UART (Universal Asynchronous Receiver Transmitter) for RF based modules, which is a type of serial communication protocol, mainly used for short-distance, low speed and low-cost data transmission between two embedded systems or computer peripherals. These days RF-Microcontroller modules widely uses UART protocol for the interface with other hardware. A reduced FSM (Finite State Machine) UART design has been implemented on different FPGAs. The maximum achievable speed and their corresponding power consumption are calculated using these FPGAs. The proposed design is implemented using Verilog HDL and for simulation purpose, Xilinx ISE 12.1, 14.7, Xilinx Vivado 2018 and Intel Quartus Prime 19.1 are used. The smallest value of maximum power consumption i.e. 20.67mW at 105.47MHz frequency with 180nm technology node is achieved by Intel Max V among all the Intel and Xilinx devices. Furthermore, the maximum achievable frequency i. e. 769.48 Hz has been found in Virtex 4 FPGA device. Xilinx Virtex UltraScale+ devices occupy the minimum area which provides 16-nm FinFET Technology node.

A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers

Temperature rising is an unavoidable effect on VLSI and has always been a critical issue in any system-on-chip &#x2013; especially when targeting compute-intensive applications. This effect increases the delay in hardware accelerators, resulting in timing errors due to unsustainable clock frequency, whose impact must be carefully evaluated on design time to measure the performance degradation of the hardware accelerator. Further, a hardware operating at a higher temperature accelerates device aging, which incurs in more timing errors. This issue is usually addressed with the inclusion of timing guardbands that compensate for the deleterious effects of temperature, ensuring the hardware accelerator works within a reliable zone, i.e., without any timing errors caused by temperature effects at runtime. However, guardbands directly result in considerable performance and efficiency losses because the circuit will be clocked at a frequency lower than its full potential. Accelerators on edge devices often dismiss such guardbands to explore the full potential of the designed circuits, posing an enormous design challenge as this approach requires a careful evaluation of the impact of timing errors on the quality of the target applications. Many algorithms, such as in multimedia and machine learning applications, are capable of tolerating hardware errors. Yet, these algorithms have a dynamic behavior (i.e., closed-loop) where a timing error can be propagated, affecting subsequent steps. Measuring the degradation-induced errors in these applications is very challenging given that an accurate gate-level simulation to investigate degradation-induced timing errors needs to be coupled dynamically with a system-level simulator to unveil how induced errors in the underlying hardware ultimately impact the algorithm execution in the hardware accelerator. <i>This is the first work to achieve this goal</i>. State-of-the-art works have studied accelerators under timing-errors when removing (or narrowing) guardbands. However, their approach was suitable <i>only for open-loop hardware accelerators which are entirely agnostic of complex interactions of the algorithms</i>. Unlike prior work, this paper investigates temperature- and aging-induced timing-errors in the joint accelerator-algorithm interactions and their runtime impacts. Our framework investigates aging effects across the different layers starting from transistor physics all the way up to the algorithm layer. The hardware accelerator employed as a case study in this work is the sum of absolute differences (SAD), which is the most compute-intensive accelerator on commercial video encoder for mobile applications. Our results demonstrate the runtime behavior impacts of three advanced block-matching algorithms of the video encoder in a joint operation by a SAD accelerator under timing-errors induced by temperature and aging effects considering a 14nm FinFET technology.

Impact of NCFET on Neural Network Accelerators

This is the first work to investigate the impact that Negative Capacitance Field-Effect Transistor (NCFET) brings on the efficiency and accuracy of future Neural Networks (NN). NCFET is at the forefront of emerging technologies, especially after it has become compatible with the existing fabrication process of CMOS. Neural Network inference accelerators are becoming ubiquitous in modern SoCs and there is an ever-increasing demand for tighter and tighter throughput constraints and lower energy consumption. To explore the benefits that NCFET brings to NN inference regarding frequency, energy, and accuracy, we investigate different configurations of the multiply-add (MADD) circuit, which is the core computational unit in any NN accelerator. We demonstrate that, compared to the baseline 7nm FinFET technology, its negative capacitance counterpart reduces the energy by 55%, without any frequency reduction. In addition, it enables leveraging higher computational precision, which results to a considerable improvement in the inference accuracy. Importantly, the achieved accuracy improvement comes also together with a significant energy reduction and without any loss in frequency.

NPU Thermal Management

Neural processing units (NPUs) are becoming an integral part in all modern computing systems due to their substantial role in accelerating neural networks (NNs). The significant improvements in cost-energy-performance stem from the massive array of multiply accumulate (MAC) units that remarkably boosts the throughput of NN inference. In this work, we are the first to investigate the thermal challenges that NPUs bring, revealing how MAC arrays, which form the heart of any NPU, impose serious thermal bottlenecks to on-chip systems due to their excessive power densities. For the first time, we explore: 1) the effectiveness of precision scaling and frequency scaling (FS) in temperature reductions and 2) how advanced on-chip cooling using superlattice thin-film thermoelectric (TE) open doors for new tradeoffs between temperature, throughput, cooling cost, and inference accuracy in NPU chips. Our work unveils that hybrid thermal management , which composes different means to reduce the NPU temperature, is a key. To achieve that, we propose and implement PFS-TE technique that couples precision and FS together with superlattice TE cooling for effective NPU thermal management. Using commercial signoff tools, we obtain accurate power and timing analysis of MAC arrays after a full-chip design is performed based on 14-nm Intel FinFET technology. Then, multiphysics simulations using finite-element methods are carried out for accurate heat simulations in the presence and absence of on-chip cooling. Afterward, comprehensive design-space exploration is presented to demonstrate the Pareto frontier and the existing tradeoffs between temperature reductions, power overheads due to cooling, throughput, and inference accuracy. Using a wide range of NNs trained for image classification, experimental results demonstrate that our novel NPU thermal management increases the inference efficiency (TOPS/Joule) by $1.33\times $ , $1.87\times $ , and $2\times $ under different temperature constraints; 105 °C, 85 °C, and 70 °C, respectively, while the average accuracy drops merely from 89.0% to 85.5%.

Power Side-Channel Attacks in Negative Capacitance Transistor

Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson's current mirror-based LS (WCMLS), CMLS-LED offers an enhanced speed by avoiding the threshold voltage drop of the feedback pFET and is free from the stability issue due to an incomplete output swing. Measurement results obtained from the test chip fabricated with 14-nm finFET technology, in which CMLS-LED is implemented with WCMLS, CPLS, and Osaki's LS, shows that the proposed CMLS-LED can widen the operating voltage range by 200 mV compared wth the CPLS, along with a speed improvement of 80%, when compared to WCMLS.

Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a $2.2\times $ improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).

Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators

Stochastic computing (SC) adopting probability as the medium, has been recently developed in the field of neural network (NN) accelerator due to simple hardware and high fault tolerance. However, traditional SC-based NN accelerators employ the bit-serial computation, and thus suffer from high latencies, random fluctuations and high hardware costs of bitstream number generators. In this brief, a novel parallel hybrid stochastic-binary-based NN (PHSB-NN) accelerator architecture manipulating the parallel thermometer coding is proposed. Parallel bitstream number generator and multiply accumulate (MAC) are also proposed, respectively, which can synchronously decode all bitstreams and complete the MAC computation in only one clock cycle. Compared with traditional SC-based NN accelerators, the proposed PHSB-NN accelerators can achieve 33.5× energy efficiency improvement without sacrificing the accuracy on the MNIST dataset, as demonstrated in the circuit synthesis results of the standard 14-nm FinFET technology.

Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology

Transistor arrangement influences the performance of logic cells. Complex logic cells can be used to minimize area, delay, and power. However, with the increasing relevance of nanometer challenges such as process variability and radiation effects, it is also necessary to consider these factors at logic level design. The main contribution of this work is to evaluate the advantages of adopting a multi-level logic design instead of using complex gates to mitigate process variability and radiation effects. A justification for choosing the parameter that will characterize process variability is presented. Also, the analysis with different transistor arrangements and sizing is carried out to provide a basis for a better understanding of the obtained results. The experimental evaluation considers two topologies: complex gates and multi-level using basic gates, for a set of logic gates using the 7nm FinFET technology at the layout level. As expected, at nominal conditions, the best choice is to adopt complex gate topology to optimize area, power consumption, and performance. However, the logic multi-level arrangements became the functions up to 50% less sensitive to the transient faults and at least 30% more robust to the process variability effects. A trade-off needs to be done, considering the area and power constraints.

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations under technology scaling lead to a reduced data retention time (DRT), resulting in increased refresh power and reduced memory availability, currently limiting its implementation to planar 28-nm technologies and above. This letter presents the first gain-cell embedded DRAM (GC-eDRAM) in 16-nm FinFET technology, featuring a mixed- $V_{T}$ 3T gain-cell structure to minimize the storage node (SN) leakage. The implemented 1-Mbit 3T GC-eDRAM is fully logic-compatible and provides a $2\times $ smaller bitcell size compared to a 6T SRAM with similar design rules, offering the highest density logic-compatible memory cell in 16-nm technology. Measurement results demonstrate a 77- $\mu \text{s}$ DRT under a 600-mV $V_{\text {DD}}$ , which is over $10\times $ longer than previously reported GC-eDRAMs in 28-nm technologies. The memory was fully operational at temperatures spanning −40 °C to 125 °C and under a supply voltage as low as 450 mV, providing the lowest measured $V_{\text {DDmin}}$ and widest temperature range reported in the literature for GC-eDRAM.

A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET

This letter introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a $4\times $ time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a $16\times 16$ -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (−27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

On the Workload Dependence of Self-Heating in FinFET Circuits

Self-heating effect (SHE) is a major reliability concern in current and upcoming technology nodes due to its ability to increase the channel's temperature of transistor and leading to degradations in the key electrical characteristics such as carrier mobility. In this brief, we study SHE in a full processor at the 7nm FinFET technology node. This is the first work to analyze the impact that executed workloads on top of processors have on stimulating SHE. As matter of fact, SHE in transistors is driven by the workload-induced switching activities. When it comes to evaluating SHE, state of the art typically assumes that the switching frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sw</sub> and operating clock frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clk</sub> of a circuit are the same, concluding that SHE is not a concern in digital circuits that operate in the GHz-range like processors. After analysis a wide range of workloads, our investigation revealed that the majority of transistors in the processor's netlist exhibit a switching frequency in the kHz-range even though the processor's clock is in the GHz-range. This is because that the majority of transistors are within the data paths and hence their switching is driven by the workload data and not by the clock itself. In addition, we also demonstrate for the first time the important role that the duty cycle (on-/off-ratio) induced by the running workload has on modeling SHE. All in all, the relatively low switching activities together with skewed duty cycles induce a wide variety in channel temperatures. Thus, highlighting the importance of considering the workload when studying SHE.

High speed, low duty cycle variation level shifter for ring oscillators

ABSTRACT A high-speed level shifter for ring oscillators is presented. It uses a tracking mechanism to reduce the duty cycle variation due to Process, Voltage, and Temperature (PVT). Extensive simulations across PVT and Monte Carlo mismatch show that the proposed level shifter can operate at up to 6GHz with maximum duty cycle degradation of ±5%. The proposed level shifter is designed in 16nm FinFET technology and works for a core supply voltage and temperature range of 0.8V ± 10% and −40ºC to 125ºC, respectively.