Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology

Abstract

Transistor arrangement influences the performance of logic cells. Complex logic cells can be used to minimize area, delay, and power. However, with the increasing relevance of nanometer challenges such as process variability and radiation effects, it is also necessary to consider these factors at logic level design. The main contribution of this work is to evaluate the advantages of adopting a multi-level logic design instead of using complex gates to mitigate process variability and radiation effects. A justification for choosing the parameter that will characterize process variability is presented. Also, the analysis with different transistor arrangements and sizing is carried out to provide a basis for a better understanding of the obtained results. The experimental evaluation considers two topologies: complex gates and multi-level using basic gates, for a set of logic gates using the 7nm FinFET technology at the layout level. As expected, at nominal conditions, the best choice is to adopt complex gate topology to optimize area, power consumption, and performance. However, the logic multi-level arrangements became the functions up to 50% less sensitive to the transient faults and at least 30% more robust to the process variability effects. A trade-off needs to be done, considering the area and power constraints.