Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators

Abstract

Stochastic computing (SC) adopting probability as the medium, has been recently developed in the field of neural network (NN) accelerator due to simple hardware and high fault tolerance. However, traditional SC-based NN accelerators employ the bit-serial computation, and thus suffer from high latencies, random fluctuations and high hardware costs of bitstream number generators. In this brief, a novel parallel hybrid stochastic-binary-based NN (PHSB-NN) accelerator architecture manipulating the parallel thermometer coding is proposed. Parallel bitstream number generator and multiply accumulate (MAC) are also proposed, respectively, which can synchronously decode all bitstreams and complete the MAC computation in only one clock cycle. Compared with traditional SC-based NN accelerators, the proposed PHSB-NN accelerators can achieve 33.5× energy efficiency improvement without sacrificing the accuracy on the MNIST dataset, as demonstrated in the circuit synthesis results of the standard 14-nm FinFET technology.