Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Abstract

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal–oxide semiconductor (NMOS) transistor or P-channel metal–oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal–oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.