Customizable logic cell design using variable body bias

Abstract

In very large scale integrated (VLSI) circuits the power dissipation increases due to the miniaturization. This motivates the designing of low power circuits with less area overhead. The method involves designing a cell in which the logic can be customized by using variable body bias. The cell is made up of variable threshold complementary metal oxide semiconductor (VTCMOS) transistors in which the body bias of both p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) is varied based on the logic function. The dynamic threshold MOS (DTMOS) and variable threshold MOS (VTMOS) methods provide low leakage compared to CMOS at low voltage but increases the delay and also it is not suitable for cascading stages. In previous methods the transistor count is similar to the conventional CMOS. By varying the body bias in VTCMOS the leakage can be reduced and the desired logic function can be achieved. The structure and the transistor count of the proposed design remains the same irrespective of the logic gates. This reduces the power dissipation and the area. The transistor count can be reduced based on the following techniques. i) Input swing ii) Resistor network iii) Truth table implementation. Each technique has its own merits and demerits. Based on the application, the technique which is best suited can be utilized. The more compact structure can be achieved with addition bias overhead.