1-bit Full Adder Research Articles

Design and simulation of efficient combinational circuits based on a new XOR structure in QCA technology

Quantum-dot cellular automata (QCA), due to its unique characteristics like low power consumption, nanoscale design, and high computing speed is considered as an emerging technology, and it can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. XOR gate has many applications in the design of digital circuits in QCA. In this paper, an efficient novel structure of XOR gate is proposed in QCA. Also, a novel 1-bit comparator circuit, 1-bit full adder, binary to gray and gray to binary convertor code based on the proposed XOR is designed and simulated using QCADesigner 2.0.3. The simulation results demonstrated that the proposed structures provide improvements compared to previous works in terms of QCA cells count, area, and circuit cost.

Ultra-efficient adders and even parity generators in nano scale

This paper suggests a single-layer 5-input majority gate (MV5) using 11 simple cells in the Quantum-Dot Cellular Automata (QCA) technology. All simulations are performed by QCADesigner 2.0.03. Moreover, the energy consumption of the suggested 5-input majority gate is calculated using the QCAPro tool. The suggested gate shows power consumption improvements by 15.69, 9.56, and 5.95% at three levels of 0.5Ek, 1Ek, and 1.5Ek compared with the best previous designs. Moreover, using the suggested gate, n-bit QCA adder and n-bit even parity generator are designed. A comparison of the cell counts in the suggested 1-bit full-adder and the 4-bit even parity generator with the best previous structures shows 35.21% and 6.12% improvements, respectively. In addition, the suggested 4-bit and 8-bit adders show 2.29%, 4.87%, 5.76% and 24.29% improvements in terms of the cell counts compared to the best designs, respectively.

Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

A Novel Coplanar Based Adder Logic Design Using QCA

Now a days, VLSI is a one of the top most technology are used in the field of electronics communication. It is used to create an integrated circuit by merging million of MOS transistor into a single chip. In VLSI, most of the transistors are design in micro scale level. Now a days people will want all materials are in compact size. So, it is necessary to design a circuit in nanoscale level. In the field of VLSI, CMOS technologies are used for designing a integrated circuit (IC) chips. But in CMOS, size that are used to designing a circuit is in micro scale level. So researcher is introducing new nanotechnology that new technology is called QCA technology. Logic function gate is a one of the fundamental components to design an any circuit in electronics communication. In this paper, novel coplanar approach to designing an efficient QCA based 4-bit full adder using XOR/XNOR logic gate is proposed. QCA Designer Version 2.0.3 simulation tools are used in this proposed method. Performance is analysed and verified to determine the capabilities of proposed full adder.

Design of non-volatile digital circuit with assuming magnetic tunneling junction and carbon nanotubes field-effect transistors devices

Power consumption has become the key constraint in electronics design, since the MOSFET threshold and hence the supply voltage can no longer be scaled. This trend calls for new device concepts such as Spintronic devices that are fundamentally different from CMOS. A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic in memory structures in conjunction with CMOS. In this paper, we present novel designs of hybrid CNTFET-MTJ circuits; AND, XOR and 1-bit full adder. The proposed CNTFET-MTJ full adder design has 20 times lower Power-delay-product (PDP) compared to the previous CMOS- MTJ full adder. Also, the delay in CNTFET-MTJ circuit is reduced 20 times compared to the CMOS- MTJ circuit.

Hybrid memristor-CMOS implementation of logic gates design using LTSpice

In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

Approximate Full Adders for Energy Efficient Image Processing Applications

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.

Integrating Two Logics Into One Crossbar Array for Logic Gate Design

Memristor-based crossbar array is one of the most promising structure for in-memory computing platforms. In a crossbar array, material implication logic (IMPLY) can be performed between different word lines or bit lines. Not-material implication (N-IMPLY) can only be performed between the bit lines. This brief demonstrates the feasibility of the execution of N-IMPLY logic between the word lines, followed by an approach for logic gate design in which two logics IMPLY and N-IMPLY are integrated into one crossbar array. Both two logics can be performed between the cells in different rows and columns within the crossbar. Six basic Boolean gates are implemented utilizing the proposed approach, with a lower number of operation steps and memristors compared to the IMPLY-only method. Moreover, a 1-bit full adder is implemented by utilizing the designed logic gates. The performance and area overhead have been improved by the proposed approach, in comparison to the existing methods.

LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS

In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72% improvement). The proposed cell simulated in HSPICE with 32nm CMOS technology in four different scenarios. First, the proposed cell was assessed as a 1-bit full adder cell; second, the proposed cell applied in a 4-bit carry ripple adder structure. In the third and fourth scenarios, the proposed cell's power consumption and performance were assessed in different power supply voltages, temperatures, and a larger load capacitor. Approximate computing is a design paradigm that is applicable in image processing as an error-resilient application. MATLAB exploited to assess the proposed approximate full adder in image addition application in three different scenarios. The outputs evaluated by different image quality metrics (such as peak signal to noise ratio (PSNR)) and the final outputs of approximation are acceptable in this application due to image quality metrics.

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

PurposeIn nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.Design/methodology/approachThis paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.FindingsA new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.Originality/valueThis paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.

Near-zero computing using NCFET for IoT applications

The energy consumption of the devices or circuits built on the IoT's is becoming a significant concern with the complementary metal oxide semiconductor (CMOS) technology scaling. To reduce energy consumption, supply voltage (VDD) scaling has proved to be an effective technique with near-threshold/subthreshold computations depicting the endpoint of voltage scaling. This paper discusses how the near-zero computing (NZC) is achieved by scaling the VDD beyond the subthreshold regime using the negative capacitance FET (NCFET) to enable IoT with beyond CMOS features. After characterising the NCFET for near zero operation, the basic computational circuits: logic gates and 1-bitfull adder circuit are designed and simulated using NCFET at near-zero VDD of 0.1 V. In comparison with the CMOS counterparts, the NCFET logic designs have achieved significant improvements and is found that the NCFET logic results in more than 54%, 68%, 85%, and 95% savings in power, delay, energy, and EDP respectively.

Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems

In this paper, we present two novel approximate Full Adder cells with capacitive threshold logic (CTL) using carbon nanotube field-effect transistor (CNFET) technology. To investigate the efficiency of the proposed cells, extensive simulations are carried out at both application and transistor levels. At the application level, by using the MATLAB tool, the proposed cells are applied to the motion detector algorithm as one of the practical image processing applications. Peak signal-to-noise ratio (PSNR) is considered as a legitimate application-level evaluating factor. In addition, by using the HSPICE tool, the hardware level parameters such as average power consumption, delay, and power-delay product (PDP) are estimated. Then, a compromise between the application and hardware-level metrics is considered. Noise analysis is also accomplished by taking noise immunity curve (NIC) and average noise threshold energy (ANTE) into account. Furthermore, Monte Carlo transient analysis is exploited to study the robustness of the introduced cells against diameter deviations of the carbon nanotubes (CNTs). Simulation results indicate the supremacy of the proposed cells compared to others.

Estimation of Leakage Power and Delay in CMOS Circuits

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

Fast and energy efficient full adder circuit using 14 CNFETs

With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (VDD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (DCNT) and threshold voltage (Vth) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.

Energy Efficient GDI Based Full Adders For Computing Applications

This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.

DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS

This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors

The physically separated memory and logic units in traditional von Neumann computers place essential limits on the performance and cause increased energy consumption, and hence in-memory computing is required to overcome this bottleneck. Here, a new bipolar memristor based in-memory logic approach is proposed, which is capable of achieving all 16 possible Boolean logic functions in a single device in less than 3 steps. This approach does not require initialization and can facilitate logic cascading, and the calculation taking place in-situ is showcased by 1-bit full adder and 2-bit multiplier with improved efficiency, thus showing a great prospect in future in-memory computing architecture.

Design of reversible universal and multifunctional gate-based 1-bit full adder and full subtractor in quantum-dot cellular automata nanocomputing

The issues faced by CMOS technology in the nanoregime have led to research for other possible technologies that can operate with the same functionalities but with higher speed and lower power dissipation. One such technology is quantum-dot cellular automata (QCA). A 3 × 3 reversible universal and multifunctional gate is presented that is reversible, universal, and multifunctional in nature. The gate is then used as a building block to design an ultra-efficient 1-bit full adder and 1-bit full subtractor in QCA. Based on the performance analysis, it is concluded that the proposed designs are efficient in respect to cell count, area, delay, and quantum cost and achieve performance improvements over existing designs in the literature. Hence, the proposed designs can be efficiently utilized in various digital logics requiring minimal area and ultra-low-power consumption such as central processing units, microcontrollers, etc.