Ultra-efficient adders and even parity generators in nano scale

Abstract

This paper suggests a single-layer 5-input majority gate (MV5) using 11 simple cells in the Quantum-Dot Cellular Automata (QCA) technology. All simulations are performed by QCADesigner 2.0.03. Moreover, the energy consumption of the suggested 5-input majority gate is calculated using the QCAPro tool. The suggested gate shows power consumption improvements by 15.69, 9.56, and 5.95% at three levels of 0.5Ek, 1Ek, and 1.5Ek compared with the best previous designs. Moreover, using the suggested gate, n-bit QCA adder and n-bit even parity generator are designed. A comparison of the cell counts in the suggested 1-bit full-adder and the 4-bit even parity generator with the best previous structures shows 35.21% and 6.12% improvements, respectively. In addition, the suggested 4-bit and 8-bit adders show 2.29%, 4.87%, 5.76% and 24.29% improvements in terms of the cell counts compared to the best designs, respectively.