Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Xinyu Chen,David Wei Zhang,Tianxiang Wu,Zeming Wang,Shunli Ma,Zhike Xue ,Zhengzong Sun,Hao Líu ,Antoine Riaud,Zihan Xu,Chenjian Wu,Ling Tong,Yaochen Sheng,Jing‐Fa Deng ,Sitong Bu,Jing Wan,Xiaojiao Guo,Jiaxin Cao,Daming Huang,Peng Zhou,Yu Wang,Fuyu Bai,Shiwei Xing,Fuyou Liao,Zengfeng Di,Hongwei Tang,Jialin Ma ,Hui Shen,Yufeng Xie,Hanqi Liu,Xiao Gong,Ye Lü ,Yin Wang,Wenzhong Bao

doi:10.1038/s41467-021-26230-x

Abstract

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.

Highlights

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated
While intrinsic advantages of 2DLMs are promising for more-than-Moore electronic applications[22,23,24,25], it is still challenging to meet the stringent requirements for large-scale circuit- and system-level applications, where the primary challenges are wafer-scale material synthesis and device processing[26,27,28,29,30,31,32,33]
It is necessary to optimize the combination of these quantities, and different device applications require different optimization strategies, e.g., a high μ is critical for faster operation speed, and a small subthreshold swing (SS) is essential for low-power consumption

Summary

Introduction

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. There are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. We overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). We present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials. With wafer-scale processing using industry-standard design flows and processes, our work illustrates the feasibility of using ML in device-processing optimization for emerging novel materials and shortens the learning cycle from fundamental research to practical application

Methods

Results

Conclusion