Abstract
The energy consumption of the devices or circuits built on the IoT's is becoming a significant concern with the complementary metal oxide semiconductor (CMOS) technology scaling. To reduce energy consumption, supply voltage (VDD) scaling has proved to be an effective technique with near-threshold/subthreshold computations depicting the endpoint of voltage scaling. This paper discusses how the near-zero computing (NZC) is achieved by scaling the VDD beyond the subthreshold regime using the negative capacitance FET (NCFET) to enable IoT with beyond CMOS features. After characterising the NCFET for near zero operation, the basic computational circuits: logic gates and 1-bitfull adder circuit are designed and simulated using NCFET at near-zero VDD of 0.1 V. In comparison with the CMOS counterparts, the NCFET logic designs have achieved significant improvements and is found that the NCFET logic results in more than 54%, 68%, 85%, and 95% savings in power, delay, energy, and EDP respectively.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.