Abstract
Abstract In this paper, an approach to increase integration rate of elements of a comparator in track state was introduced. Framework the approach a het-erostructure with special configuration was consider. Several specific are-as of the heterostructure should be doped by diffusion or ion implantation. Annealing of dopant and/or radiation defects should be optimized.
Highlights
An actual and intensively studied topic in solid-state electronics is the need for increasing the integration rate of elements of integrated circuits (p-n-junctions, their systems, etc.) [1,2,3,4,5,6,7,8]
The heterostructure consists of a substrate and several epitaxial layers
The doping gives a possibility to manufacture sources (S), gates (G), and drains (D) of field-effect transistors framework the considered comparator in track state so as it is shown on Figure 1
Summary
An actual and intensively studied topic in solid-state electronics is the need for increasing the integration rate of elements of integrated circuits (p-n-junctions, their systems, etc.) [1,2,3,4,5,6,7,8]. Using the approaches gives a possibility to increase integration rate of elements of integrated circuits through inhomogeneity of technological parameters due to generating inhomogenous distribution of temperature In this situation, one can obtain decreasing dimensions of elements of integrated circuits [18], with taking into account the Arrhenius law [1, 3]. Another approach to manufacture elements of integrated circuits with smaller dimensions is doping of heterostructure by diffusion or ion implantation [1,2,3] In this case, optimization of dopant and/or radiation defects is required [18].
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