Abstract

In this paper we present an approach for combining on-line concurrent checking (CC) with off-line built-in self-test (BIST). We will show that a reduction of an aliasing probability can be obtained for manufacturing testing by monitoring the output of a concurrent checker and a reduction of a probability of not detecting an error in the computing mode can be obtained by a short periodic BIST. We will present a technique for optimal selection of error-detecting codes for combined on-line CC and off-line space-time compression of test responses for BIST and estimate probabilities of not detecting an error for the approach based on integrating CC and BIST. We also present a technique for on-line error-detection in space-time compressors of test responses for BIST.

Highlights

  • Off-line testing techniques such as Built-In Self-Test (BIST) and boundary scan have been the focus of VLSI test engineers concerned with product quality

  • If a (n, s, d) code Vsc is used for space compression, the corresponding SC can be constructed from XOR gates only, the SC has m n s outputs (m

  • Example 1 To illustrate the relations between offline space-time compression of test responses, online CC and the corresponding codes Vsc, Vrc and Vcc let us consider the case when the original device, D, is the control ROM for MC68020

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Summary

Mechanisms in the Coding Theory Framework

In this paper we present an approach for combining on-line concurrent checking (CC) with off-line built-in self-test (BIST). We will show that a reduction of an aliasing probability can be obtained for manufacturing testing by monitoring the output of a concurrent checker and a reduction of a probability of not detecting an error in the computing mode can be obtained by a short periodic BIST. We will present a technique for optimal selection of error-detecting codes for combined on-line CC and off-line space-time compression of test responses for BIST and estimate probabilities of not detecting an error for the approach based on integrating CC and BIST. We present a technique for on-line error-detection in space-time compressors of test responses for BIST. Keywords." Built-in self-test, on-line detection, space-time compression of test responses, multipleinput linear feedback registers, error detecting codes

INTRODUCTION
Signature to be verified
Missi o n Inputs
Predictor for TC
Parity Predictor
Let us denote the check matrix for this code as
Parity Predictor for SC
CONCLUSIONS
Findings
Finite Orthogonal Series in the design of Computer
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