Optimal design of checksum-based checkers for fault detection in linear analog circuits

Abstract

Traditionally, built-in self-test (BIST) techniques have assumed access to only the input and output nodes of the circuit under test (CUT). It has been shown earlier, that checksum-based checkers can be designed to perform on-line fault detection in linear analog circuits using access to certain internal nodes of CUT. In this paper, we address the problem of optimizing the checker circuitry to maximize the detectability of faults in CUT. The above optimization problem is solved as a linear programming problem. The resulting checker can be used to perform both BIST of CUT and on-line error detection as well. Faults in the checker hardware are taken into account during the checker optimization process.