A low power architecture for online detection of execution errors in SMT processors

Abstract

In highly scaled nano-CMOS devices, soft errors and aging defects are a design concern. Online detection of errors is necessary to address such errors. For online error detection in microprocessors, redundant execution of the entire pipeline has been studied. Software solutions for such re-execution impose significant performance penalty due to competition for execution resources between the main and the redundant threads, while hardware implementations incur large area overhead. Previously, researchers have proposed alternative low-cost mechanisms targeting only the execution stage of the processor pipeline. Earlier work, however, (i) neglects the effect of such redundant execution in simultaneous multi-threaded processors, (ii) neglects the energy overhead of such redundant execution and (iii) only focus on soft error detection, while neglecting detection of hard errors. In this paper, we extend the earlier work by addressing these shortcomings. Our studies indicate that prior solutions are either energy or performance efficient, but not both. Towards this end, we explore a hybrid scheme based on earlier work that is both energy and performance efficient. Results indicate that such a hybrid scheme may result in performance and energy improvement of 5% when compared to earlier solutions. This is a significant improvement since unlike previous schemes, the proposed scheme enables detection of both soft and hard errors.