Abstract
This chapter presents a discussion on the designs and implementations of networks on chip (NoC)-based systems-on-chips (SoCs). NoC architectures are emerging as a strong candidate for the highly scalable, reliable, and modular on-chip communication infrastructure platform to implement high-performance SoCs. The chapter introduces the silicon chip implementation trials for NoC-based SoCs. The chapter discusses both academic and industrial design efforts, even though academic designs are dominant. This is because NoC technology is maturing and for the time being commercial SoC products have relied on mature and well-established bus-based interconnects. In academia, KAIST's BONE series are explained as the typical example to make the NoC practical. It also explains various NoC implementation issues such as low power, synchronization, and high-speed signaling techniques. The chapter highlights three NoC-based experimental systems—Berkeley's Pleiades processor, MIT's Raw machine, and STMicroelectronics' multistage reconfigurable crossbar architecture—as other trials of NoC implementation.
Published Version
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