Abstract
Network-on-chip (NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet- switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project ,we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is uded to reduce network routing time, and it is an suitable alternate to network design and implementation. The cartesian Network-On-Chip can be modelled using Verilog HDL and simulated using Modelsim software&Quartus II. Keywords: Network-on-Chip (NoC), Routing, Switching, Cut-through,Cartesian
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