Chapter 1 - Networks on Chip

Abstract

This chapter presents a discussion on networks on chips (NoCs). This integrated microprocessor has been a landmark in the evolution of computing technology. Whereas it took monstrous efforts to be completed, it appears now as a simple object to us. Indeed, the microprocessor involved the connection of a computational engine to a layered memory system, and this was achieved using busses. Complex application-specific integrated circuits (ASICs) were designed to address-specific applications. These systems required multiprocessing over heterogeneous functional units, thus requiring efficient on-chip communication. On the other side, multiprocessing platforms were developed to address high-performance computation—such as image rendering. Furthermore, the chapter explains variability and design methodologies of NoCs. Dealing with variability is an important matter affecting many aspects of systems-on-chips (SoC) design. The first important issue deals with malfunction containment. Traditionally, malfunctions are avoided by putting stringent rules on physical design and by applying stringent tests on signal integrity before tape out. This approach is conservative in nature and leads to a perfect physical layout of circuits.