Chapter 6 - Network Interface Architecture and Design Issues

Abstract

This chapter presents a discussion on network interface architecture and design issues. Network interfaces (NIs) are usually denoted as the glue logic necessary to adapt communicating cores to the on-chip network. Embedded system processors are natively designed with bus-specific interfaces. As a result, hardware sub-modules of communication architectures are directly exposed to core interfaces. An important issue while creating packets or dividing them up into flits is selecting packet length and flit size. Almost all NIs try to tailor the packet length to the specific network transaction to be carried out. The chapter explains NI design issues and architectural tradeoffs in a structured way. The main services offered by the NI are discussed with the main components of its architecture—namely, the standard interface socket, the packing stage, and the buffering and flow control stage. For each component, besides addressing implementation issues and the trade-offs spanned by the configuration space, the impact of NI on the overall system complexity and performance is also described in the chapter. In fact, design choices made at the NI affect switching element design strategies and even system-level performance and power dissipation, thus making the point for communication-centric design.