Design of a low latency network interface using dual buffer for network on chip

Abstract

Recently, Network-on-Chip (NoC) paradigm has been known as a promising solution for complex Systems-on- Chip (SoC) design. A network interface is a significant part of a NoC. The network interface operates like a bridge between processing resources and network routers. This paper presents a new network interface design using parallel writing and reading buffers. The network interface architecture is modeled using Verilog HDL and implemented targeting Xilinx Virtex-6 board. The experimental results prove that our network interface design can obtain stability, reduce average latency of the packet up to 25.1 % and have a higher speed compared to an architecture that uses one normal FIFO buffer for both reading and writing processes.