Abstract
This chapter discusses the power dissipation problem in the very-large-scale integration (VLSI) industry in general, and in field programmable gate arrays (FPGAs), in particular. The tremendous growth of the semiconductor industry in the past few decades is fueled by the aggressive scaling of the semiconductor technology following Moore's law. As a result, the industry witnessed an exponential increase in the chip speed and functional density with a significant decrease in power dissipation and cost per function. However, as complementary metal oxide semiconductor (CMOS) devices enter the nanometer regime, leakage current is becoming one of the main hurdles to Moore's law. According to Moore, the key challenge for continuing process scaling in the nanometer era is leakage power reduction. Thus, circuit designers and CAD engineers have to work hand in hand with device designers to deliver high-performance and low-power systems for future CMOS devices.
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