Chapter 5 - Leakage Power Reduction in FPGAs Using MTCMOS Techniques

Abstract

This chapter presents supply gating techniques in field-programmable gate arrays (FPGAs) through the use of multithreshold CMOS (MTCMOS) approaches for subthreshold leakage power reduction. It discusses a modified FPGA architecture with sleep transistors and the CAD algorithms needed to benefit from the architecture changes. It introduces a new activity profiling phase in the CAD flow to identify the blocks that exhibit similar idleness to collectively turn them OFF during their idle times. It presents a new packing technique to pack those blocks with similar activity profiles together to easily turn them OFF. In FPGA designs, leakage power reduction has been overshadowed by performance improvements and dynamic power minimization techniques. However, recently, leakage power started to gain increased attention by both FPGA circuits and CAD designers. The leakage power dissipation problem is more crucial in FPGAs compared to custom ASIC designs because of the unutilized resources in FPGAs. On average, the percentage utilization of resources in FPGAs is approximately 60%. Thus, almost 40% of the FPGA consumes standby leakage power without delivering useful output. Moreover, FPGAs used in wireless applications can go into idle mode for long periods of time. In such designs, even the utilized resources need to be forced into a low-power (standby) mode during their idle periods to save leakage power.