Chapter 4 - Dynamic Power Reduction Techniques in FPGAs

Abstract

This chapter discusses the main techniques proposed in the literature for dynamic power reduction in field programmable gate arrays (FPGAs). The dynamic power reduction techniques can be categorized as circuit, architecture, or CAD techniques. Glitches occur due to unbalanced paths of inputs to combinational circuits. The most straightforward method of reducing glitches is to delay the fast input signals such that they have the same arrival times as slow input signals. Adding an extra delay element before the fast input, which is equivalent to the difference in arrival times of the two input signals, eliminates the glitch at the output. The delay element is composed of two-stage inverters, where the first one has programmable pull-up and pull-down resistors that are controlled by configuration SRAM bits. Adding such programmable delay elements to an FPGA architecture results in increasing the area as well as power dissipation of the FPGA. Hence, designers should be aware of the trade-offs involved in adding such programmable delays, or else the power savings will end up being consumed by the added delay elements.