ZnO TFT Research Articles

On-Current Improvement in Bulk-Accumulated Double-Gate ZnO TFT

On-Current Improvement in Bulk-Accumulated Double-Gate ZnO TFT

ZnO-based triboelectric nanogenerator and tribotronic transistor for tactile switch and displacement sensor applications

Tribotronics, the coupling of triboelectricity and semiconductors, is a novel field that has sparked much interest in the nanoelectronics and nanoenergy industries. This work presents the fabrication of a ZnO tribotronic transistor by combining a ZnO thin film transistor (ZnO-TFT) and a triboelectric nanogenerator (TENG) operating in vertical contact separation mode. A Si/SiO2/ZnO/Au structure was used to construct a bottom-gated ZnO-TFT. Radiofrequency (RF) magnetron sputtering was employed to deposit ZnO thin film, and the Au contact was achieved through thermal evaporation. A range of annealing temperatures was investigated, and ZnO TFT annealed at 500 °C exhibited a maximum electron mobility of 5.47 cm2/V s and a high on/off ratio of 105. We also investigated the photoresponse of this optimized ZnO-TFT using a UV LED. A vertical contact separation mode TENG was fabricated using ZnO (tribo-positive layer) and polyvinylidene difluoride (PVDF, tribo-negative layer) and combined with the ZnO TFT to fabricate a tribotronic transistor. The drain current of the tribotronic transistor dropped from 2.9 to 0.02 µA at a drain voltage of 5 V when the tribo layers were separated by 15 mm. Within the separation region of 2 mm, the device showed a 1.29 µA/mm change in drain current demonstrating its effectiveness in displacement sensing. Unlike conventional TFTs, the TENG's output could successfully control the tribotronic transistor's drain current and was innovative in such domains where conventional electrical components were constrained. Furthermore, this ZnO tribotronic device was used as an active smart tactile switch by simply touching or releasing the ZnO TENG with a finger.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Improvement of electrical properties of ZnO TFT with NbLaO-based stacked gate dielectrics

The double-stacked gate dielectrics (DSGD), which consisted of either NbLaO/Al2O3 or NbLaO/SiO2, were used to improve the electrical performance of zinc oxide thin-film transistor (ZnO-TFT) with single-layer NbLaO gate dielectric (SLGD). Compared to ZnO-TFT with SLGD, the ZnO-TFTs with DSGD exhibit better electrical performance, specifically for the device with the NbLaO/SiO2 DSGD, with an increase of the field-effect mobility from 5.77 cm2V[Formula: see text]s[Formula: see text] to 39.64 cm2V[Formula: see text]s[Formula: see text], an enhancement of the on/off current ratio by two orders of magnitude, a reduction of the subthreshold slope from 110 mV/decade to 70 mV/decade. The performance enhancements are attributed to a low root-mean-square surface roughness of less than 0.3 nm and a low trap-state density of less than [Formula: see text] cm[Formula: see text] (even [Formula: see text] cm[Formula: see text] for the NbLaO/SiO2 DSGD) in the bulk of the channel and at the ZnO/NbLaO interface. The results imply that ZnO-TFTs with DSGD have the potential for the application of high-resolution flat panel display.

(Invited) Vertical Transparent ZnO TFT Based on a Stack of Thin-Films Deposited in Solution

A lot of works are devoted now to integrate driving TFT with OLED, minimizing the area of the pixel. In other part, people try to fabricate devices using low cost technologies as deposition in solution avoiding any photolithography step in the process. Finally, it can be better if the full driving TFT-OLED device is transparent.The present work try to answer simultaneously to these 3 desires. Particularly, the present paper focus on the TFT.Vertical TFT will answer to the first desire to minimize the area of the device. It is based here on a stack of the gate, the insulator, the source, the semiconducting active layer and the drain; meaning 5 films all solution deposited.Thanks to the present available insulator solutions for the deposition, different insulators can be chosen. High k HFO2 insulator is chosen in this work. It is is spincoated and then annealed at 300C during 1 hour. Figure 1 shows the current-voltage curves of ITO/HFO2/AgNWs stack. After rapid increase, the current stabilizes at 10 pAmp at least still a voltage of 10V, meaning a field of 7.7x105 V/cm2 with a thickness of 130 nm. Present HFO2 film is then a good insulator.ZnO is chosen as active layer. It is spin-coated and then annealed at 180C. This temperature was found enough high to lower the conductivity (Figure 2)The source and drain layers are spin-coated using Ag nanowires (AgNWs) solution. As source AgNWs layer is deposited before ZnO layer, it will be annealed at the same temperature 180C. Figure 3 shows that AgNWs film stays enough conducting after such annealing temperature. It can be used as conducting source and drain.Finally, the full stack of 5 films is characterized as a TFT.Figure 4 shows the transfer characteristic of this TFT plotted at a drain voltage of 2.6V. The drain current is modulated by 4 orders from off to on regime.Very simple and low cost fully in solution process is presented in this work. Working transparent TFT is demonstrated. The process shows its high potential in the development of integrated TFT-OLED in small area. It is very promising.Its shows also the need of future hard work in this way to demonstrate fully integrated driving TFT-OLED Figure 1

Design and investigation of [formula omitted] based thin film transistors for high-speed AMLCD pixel circuit applications

The present paper reports a detailed comparative study of ZnO TFT with its two materials doped variants i.e., CdxZn1−xO &MgyZn1−yO. Three TFT structures are taken into consideration whose performances are explored in terms of analog, radio-frequency (RF), linearity, energy efficiency and noise analysis using a TCAD simulator. Further successful implementations of these TFT structures are done on an AMLCD pixel circuit. Tremendous improvement was observed in all the devices as well as circuit performance after material doping of Cd and Mg in ZnO. In device analysis, CdxZn1−xO TFT demonstrated superior current drive (ION/IOFF), subthreshold swing (SS) and mobility (μeff&μFE) to other structures, however with minor increase in kickback voltage in pixel circuit and vast decrease in time circuit delay. Percentage improvement in (ION/IOFF) ratio, effective mobility (μeff) and field mobility (μFE) for CdxZn1−xO based TFT are found to be ∼9041%, 196% and 111% with respect to ZnO TFT, whereas for MgyZn1−yO the improvements are ∼8253%, 136% and 105% only. At the same time percentage decrease in subthreshold swing and pixel circuit delay for CdxZn1−xO based TFT are ∼38% and ∼98% as compared to ZnO TFT, and the corresponding decrements for MgyZn1−yO are ∼3% and 92% respectively. With enhanced device and circuit performance, CdxZn1−xO has come up as promising channel material in TFT in view of low power high speed display circuit applications.

A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer

Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumption. In this experiment, the RRAM device is fabricated, and its IGZO (memory) layer is deposited with AP-PECVD technique which can reduce cost of the process. Microwave annealing (MWA) is used to enhance electrical characteristics of the RRAM device (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In-Ga- Zn-O TFT. Thin Solid Films, 520, pp.1489-1494). Experiment results show that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics under bipolar operation, all forming/set/reset voltage for RRAM device is simultaneously lowered.

The influence of low indium composition ratio on sol–gel solution-deposited amorphous zinc oxide thin film transistors

In this work, we examined the influence of In doping on the morphological and structural characteristics of ZnO active layers grown by the spin coating and the electrical performance of ZnO-based thin film transistors. XRD results indicated that the active layers were amorphous due to the absence of any sharp peaks. XPS analysis was carried out to determine indium amounts as an atomic percentage in ZnO and oxidation state of In. AFM images indicated that the roughness of the active layers decreased with increasing indium concentration in ZnO. The indium doping has dramatically improved the electrical parameters of ZnO-based transistors. The field-effect mobility of undoped TFT increased ~ 157 times by adding %3 In content. The highest field-effect mobility (μsat) of 12.9 cm2V−1 s−1 was obtained for %3 In-doped ZnO TFT (IZO3). Also IZO3 has a 6.96 V threshold voltage (Vth), 106Ion/Ioff ratio, 1.98 V/dec subthreshold slope (SS), and a high on-current of 4.6 mA. We ascribed the performance enhancement of devices with In doping due to increasing carrier concentration of channel. These results show that the low concentration of indium incorporation is very crucial to change the morphological properties of ZnO active layers and to obtain high-performance solution-processed TFTs.

Effect of annealing of NbLaO dielectric on the electrical properties of ZnO thin-film transistor

ZnO thin-film transistors (ZnO TFTs) with high-k NbLaO as a gate dielectric were fabricated on an indium tin oxide (ITO)-coated glass substrate. The NbLaO film was prepared by the sputtering method at room temperature and then annealed in N2 at 200, 300, and 400 °C. The effect of annealing temperature on the quality of NbLaO and ZnO films, especially on the electrical properties and the bias-stress stability of the ZnO TFT, was investigated. The AFM images reveal that the NbLaO film annealed at 300 °C exhibits a relatively smooth surface morphology with a root mean square roughness of 0.31 nm. AFM and x-ray diffraction measurements confirmed that the grain size of ZnO thin films slightly decreases with the increase of the annealing temperature. Except the mobility of slightly less than that of the device annealed 200 °C, the other electrical properties (off-state current, on/off current ratio, and subthreshold slope) of the ZnO TFT annealed at 300 °C are better than those of the samples annealed at 200 and 400 °C and show excellent gate-bias stress stability, which is due to a combination effect of a smoother interface, a denser structure, and the absence of indium doping in the NbLaO gate dielectric, thus resulting in a lower interfacial trap density.

ZnO Thin Film Transistor: Effect of Traps and Grain Boundaries

Recently ZnO has drawn a lot of attention in semiconductor industry due to its interesting features. High exciton binding energy, high resistivity against radiation, high breakdown voltage, low temperature deposition are some of the interesting features of this material. Zinc oxide TFT device gains an increasing interest for its potential in sensing applications due to its biocompability, chemical stability and simple fabrication process with various methods and high surface-to-volume ratio. However, ZnO TFT devices from previous work exhibited poor ION and field effect mobility. This work investigates the cause of its poor performance by focusing only two factors: traps and defects in the channel and grain boundary. The work was performed in Silvaco TCAD 2D simulator. It was found that a single grain boundary in the channel causes a reduction of the ION by 95%. The effect in the ION is less severe when traps and defects were introduced in the ZnO channel. The results can assist in optimizing the TFT device performance for sensing applications.

Perspective of zinc oxide based thin film transistors: a comprehensive review

PurposeThe purpose of this paper is to present a comprehensive review on development and future trends in zinc oxide thin film transistors (ZnO TFTs). This paper presents the development of TFT technology starting from amorphous silicon, poly-Si to ZnO TFTs. This paper also discusses about transport and device modeling of ZnO TFT and provides a comparative analysis with other TFTs on the basis of performance parameters.Design/methodology/approachIt highlights the need of high–k dielectrics for low leakage and low threshold voltage in ZnO TFTs. This paper also explains the effect of grain boundaries, trap densities and threshold voltage shift on the performance of ZnO TFT. Moreover, it also addresses the challenges like requirement of stable p-type ZnO semiconductor for various electronic applications and high value of ZnO mobility to meet growing demand of high-definition light emitting diode TV (HD-LED TV).FindingsThis review will motivate the readers to further investigate the conduction mechanism, best alternate for gate-dielectric and the deposition technique optimization for the enhancement of the performance of ZnO TFTs.Originality/valueThis is a literature review. The technological evolution of TFT in general and ZnO TFT in particular is presented in this paper.

Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

A bottom-gate zinc-oxide thin-film transistor (ZnO TFT) with high-k NbLaO as gate dielectric was fabricated on indium tin oxide-coated glass substrate by radio frequency sputtering. The NbLaO gate dielectric was annealed in N2 at different temperatures (200 °C, 300 °C, and 400 °C) for 30 min to investigate the effects of the annealing temperature on the electrical properties of the device. It is demonstrated that the ZnO TFT annealed at 300 °C exhibits the relatively good electrical performance with mobility of 20.5 cm2 V−1 s−1, off-state current of 3.4 pA, subthreshold slope of 0.18 V/decade, on/off current ratio of 6.25 × 107 and small hysteresis, which are due to reduction of deep traps in the high-k film or at gate-dielectric/semiconductor interface as supported by using a low-frequency noise analysis.

A sol-gel preparation of ZnO/graphene composite with enhanced electronic properties

ZnO/graphene composite thin film was deposited through a sol-gel process. The thin film crystal structure was characterized by XRD, the result showed that the presence of graphene did not destroy the crystal structure of ZnO. The optical spectrum showed that the introduction of graphene into ZnO did not bring an obvious effects on optical properties. To further investigate the thin film properties, ZnO and ZnO/graphene thin film transistors were fabricated and characterized. The device characterization results show that ZnO/graphene TFT has maintained a high ON/OFF ratio while the field-effect mobility is more than twice increased over ZnO TFT.

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor**Projected supported by the National Natural Science Foundation of China (Grant Nos. 61076113 and 61274085), the Natural Science Foundation of Guangdong Province (Grant No. 2016A030313474), and the University Development Fund (Nanotechnology Research Institute, Grant No. 00600009) of the University of Hong Kong, China.

Si-doped zinc oxide (SZO) thin films are deposited by using a co-sputtering method, and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures. The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated. Moreover, the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure. The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm–800 nm, and the optical band gap of the SZO film gradually increases with increasing Si content. The Si-doping can effectively suppress the grain growth of ZnO, revealed by atomic force microscope analysis. Compared with that of the undoped ZnO TFT, the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10−12 A, and thus the on/off current ratio is increased by more than two orders of magnitude. In summary, the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 106 and superior stability under gate-bias and drain-bias stress.

Zinc Oxide Thin Film Transistors: Advances, Challenges and Future Trends

This paper presents a review on recent developments and future trends in zinc oxide thin film transistors (ZnO TFTs) together with challenges involved in this technology. It highlights ZnO TFT as next generation choice over other available thin film transistor technology namely a – Si: H (amorphous hydrogenated silicon), poly-Si (polycrystalline silicon) and OTFT (organic thin film transistor). This paper also provides a comparative analysis of various TFTs on the basis of performance parameters. Effect of high –k dielectrics, grain boundaries, trap densities, and threshold voltage shift on the performance of ZnO TFT is also explained.

Investigations on high-κ dielectrics for low threshold voltage and low leakage zinc oxide thin-film transistor, using material selection methodologies

This paper presents the investigations on high-κ dielectrics for low operating voltage and low leakage zinc oxide thin film transistor (ZnO TFT) using three material selection methodologies namely Ashby, technique for order preference by similarity to ideal solution (TOPSIS) and VlseKriterijumska Optimizacija I Kompromisno Resenjein in Serbian (VIKOR). Various material properties such as dielectric constant, conduction band offset to ZnO, band-gap and temperature coefficient mismatch of high κ to ZnO are investigated to find out the most promising gate dielectric material. The analysis concludes that lanthanum oxide (La2O3) is the most promising gate dielectric material for ZnO TFT transistor. The result shows a good agreement between Ashby’s, TOPSIS and VIKOR approaches.

Paper No P12: Transparent Conductive Electrode Based on Hydrogen Doped Zinc Oxide for OLED Application

AbstractA transparent and conductive electrode based on hydrogen (H) doped ZnO has been proposed for active‐matrix (AM) display applications. With optimal H plasma power and treat time, the resultant ZnO:H exhibits a low sheet resistance of 200 ohm/sq at a thickness of 150 nm. The demonstrated transparent and conductive ZnO:H can serve as electrode for LCD or OLED as well as S/D electrode for ZnO TFT. With proposed ZnO:H electrode, two photomask steps can be reduced in the fabrication of ZnO TFT‐based AM backplanes.

双有源层结构掺硅氧化锌薄膜晶体管的电特性

In order to reduce the off-state leakage current and increase the on /off current ratio in ZnO thin-film transistor(ZnO-TFT),Si-doped ZnO thin-film transistors(SZO-TFTs) and TFT with SZO /ZnO acted as dual-active-layer were fabricated by magnetron sputtering method. Effects of silicon concentration on optical transmittance of Si-doped ZnO thin film and electrical properties of SZO-TFT were investigated. Moreover,the electrical characteristics of the TFT with SZO /ZnO acted as dual-active-layer were compared with those of the TFTs with ZnO and Si-doped ZnO acted as single-active-layer. The experimental results indicated that,compared with undoped ZnO-TFT,the offstate leakage current of SZO-TFT reduces by more than two orders of magnitude,down to 1. 5 ×10-12 A,and the on /off current ratio increases by more than two orders of magnitude with a maximum value up to 7. 97 × 106; The SZO/ZnO dual-active-layer architecture used in the ZnO-based TFT could increase the on /off current ratio by about two orders of magnitude with no reduction in carrier mobility,and thus optimize the performance of the ZnO-based TFT.

UV‐Assisted Low Temperature Oxide Dielectric Films for TFT Applications

Solution-based oxide gate dielectric layers are prepared from metal nitrates using UV-assisted annealing at 150 °C. The leakage current densities of ZrO2 and Al2O3 dielectrics are less than about 10-9 A/cm2 at 1 MV/cm and comparable to those formed by annealing at higher temperatures. High dielectric constants and the low leakage current behavior of the dielectric layers provide excellent ZnO TFT performance, with a field effect mobility of 1.37 cm2/V.s and an off-current density of 10-12 A/cm2. This low fabrication temperature process is compatible with future plastic electronics technology.