Y-function Method Research Articles

Detailed electrical characterization of 200 mm CMOS compatible GaN/Si HEMTs down to deep cryogenic temperatures

A detailed electrical characterization and transistor parameter extraction on 200 mm CMOS compatible GaN/Si HEMTs was performed down to deep cryogenic temperatures. The main transistor parameters (threshold voltage Vth, low-field mobility μ0, subthreshold swing SS, source-drain series resistance Rsd) were extracted in linear region using the Y-function and the Lambert-W function methods for gate lengths down to 0.1 µm. The Y-function method was also employed in saturation region for the extraction of the saturation velocity. The results indicate that these GaN/Si HEMT devices demonstrate a very good functionality down to very low temperature with improvement of mobility and subthreshold slope. It was also shown by TLM analysis that the source-drain series resistance Rsd is more limited by the contact resistance than by the 2DEG access region resistance as temperature is lowered.

Two‐Dimensional Tellurene Transistors with Low Contact Resistance and Self‐Aligned Catalytic Thinning Process

AbstractTwo‐dimensional (2D) tellurene (Te) has shown its great potential in nanoelectronics for its high carrier mobility and air stability. However, the high‐resistance electrical contact and relatively thick Te channel hinder its ultimate scaling and device performance. Here, the transport property of Te field‐effect transistors using platinum (Pt) contact with high work function is studied, which facilitates the effective hole injection in the p‐type Te channel. The electrical contact to Te using the Y‐function method (YFM) and the transmission line method (TLM) is investigated. The Te transistors with Pt contact show a low contact resistance of 400 Ωµm, a short transfer length of 80 nm, and low specific contact resistivity of 3.2 × 10−7 Ωcm2, resulting from the low Schottky barrier height (SBH) of Pt/Te interface. The Pt electrode also can work as an efficient catalyst that allows reduction of the Te channel thickness with a controllable thinning process in water under white light illumination. This self‐aligned catalytic thinning process enables the construction of the transistors with a thin Te channel and thick Te contact with Pt metal electrodes, which provides a device configuration with both effective electrostatic control and low contact resistance.

Gaps in the Y-Function Method for Contact Resistance Extraction in 2D Few-Layer Transition Metal Dichalcogenide Back-Gated FETs

Y-Function method is often used for 2D TMD back-gated FETs, attributed to its simplicity and the lithographic challenges in processing transfer length method (TLM) test structures over 2D TMD flakes. While the contact resistance extracted from the Y-Function method was shown to be comparable to the TLM method in an early work, its applicability was never tested rigorously for the entire experimental range of 2D TMD FETs. This work presents the limitations and failure conditions of the Y-Function method when used for extracting contact resistance in back-gated, few-layer TMD FETs. We have found that the Y-Function method does not apply to the entire experimental range, such as ohmic/Schottky barrier, source-drain electric field, contact resistance, etc., particularly for the layered material-based FETs. The influence of the Schottky barrier and drain bias is investigated thoroughly for four different 2D materials (MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , MoSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). The experimental findings are then used to narrow down extraction window/conditions for the Y-Function method, which gives contact resistance estimation closer to TLM based approach for few-layer, back-gated TMD FETs.

Extraction of intrinsic contact resistance in organic thin-film transistors with single channel length and high capacitance density

Accurate characterization of the intrinsic contact resistance is important for the optimization of organic thin-film transistors (OTFTs), especially in devices with high gate capacitance density. This study reports on a method for the extraction of the intrinsic, or gate-voltage independent, contact resistance from OTFTs. In contrast to the transfer length method (TLM), this method can be applied to devices with single geometry. The method is an extension of the previously reported Y-function method and combines the model proposed by Luan and Neudeck to analyze the effect of the gate voltage on the contact resistance. This method is first applied to OTFTs with a bottom-gate top-contact geometry having varying gate capacitance density values. The intrinsic contact resistance is found to decrease with increased gate capacitance density with values ranging between 4 kΩ cm and under 1 kΩ cm when the gate capacitance is changed from 36.6 to 231.7 nF/cm2, respectively. These values are in good agreement with those obtained using TLM experiments. This method is also shown to be applicable to OTFTs with top-gate bottom-contact geometry.

Enhanced performance of multilayer MoS2 transistors encapsulated with a photoresist

We report the enhanced performance of multilayer MoS2 transistors by AZ® 5214E photoresist encapsulation. The MoS2 transistors with SiO2 bottom-gate dielectrics exhibited an average increase of 4× in the on/off-current ratio and a 50% increase in the field-effect mobility after photoresist encapsulation. The Y-function method further showed a decrease of 87% in the contact resistance and a 30% increase in the intrinsic carrier mobility, suggesting that photoresist encapsulation provides not only n-type doping but also dielectric screening. The Raman spectra of the photoresist-encapsulated MoS2 also suggest n-type doping, which may be due to the electropositive hydroxyl groups in the photoresist. The operation of the photoresist-encapsulated MoS2 transistors remained stable in ambient air for at least one month. These results demonstrate that simple photoresist encapsulation can be an effective performance booster of MoS2 and other transition metal dichalcogenides transistors.

Layer thickness influenced irradiation effects of proton beam on MoS2 field effect transistors

We investigated the influence of the flake thickness for molybdenum disulfide (MoS2) field effect transistors on the effect of a 150 keV high-energy proton beam applied on these devices. The electrical characteristics of the devices with channel thicknesses ranging from monolayer to bulk were measured before and after proton irradiation with a proton fluence of 5 × 1014 cm−2. The subthreshold swing (SS), threshold voltage shift and electron mobility were extracted with the Y-function method after proton irradiation and significant degradation were observed. It is found that, with the increase of layer thickness, mobility degradation and threshold voltage shift both eased, but the SS degradation was insensitive to the MoS2 flake thickness increase. We also demonstrate that the threshold voltage shift is dominated by oxide charges; however, the mobility and SS degradations are mainly affected by the interface traps. Our study will enhance the understanding of the influence of high-energy particles on MoS2-based nano-electronic devices. By increasing the MoS2 flake thickness to a certain extent, one can hopefully find a balance between effectively resisting shift and achieving high mobility and small SS degradation.

Metal-Contact Improvement in a Multilayer WSe2 Transistor through Strong Hot Carrier Injection.

Hot carrier injection (HCI), occurring when the horizontal electric field is strongly applied, usually affects the degradation of nanoelectronic devices. In addition, metal contacts play a significant role in nanoelectronic devices. In this study, Schottky contacts in multilayer tungsten diselenide (WSe2) field-effect transistors (FETs) by hot carrier injection (HCI), occurring when a high drain voltage is applied, is investigated. A small number of hot carriers with high energy reduces the Schottky barrier height and improves the performance of FETs effectively rather than damaging the channel. Thermal annealing at the end of the fabrication process increases device performance by causing interfacial reactions of the source/drain electrodes. HCI causes a significant enhancement in the local asymmetry, especially in the subthreshold region. The subthreshold swing (SS) of the thermally annealed FETs is significantly improved from 9.66 to 0.562 V dec-1 through the energy of HCI generated by a strong horizontal electric field. In addition, the contact resistances (RSD), also called series resistances, extracted by a four-probe measurement and a Y-function method were also improved by decreasing to a 10th through the energy of HCI. To understand the asymmetrical characteristics of the channel after the stress, we performed electrical analysis, electrostatic force microscopy (EFM), and Raman spectroscopy.

Contact resistance assessment and high-frequency performance projection of black phosphorus field-effect transistor technologies

In this work, an evaluation of the contact quality of black phosphorus field-effect transistors from different technologies previously reported is performed by means of an efficient and reliable contact resistance extraction methodology based on individual device practical characteristics. A good agreement is achieved between the extracted values with the Y-function method used here and reference values obtained with other methods considering internal values as well as with more expensive methods involving fabricated test structures. The method enables a direct evaluation of different steps in the same technology and it embraces the temperature dependence of the contact characteristics. Channel phenomena have no impact on the extracted contact resistance values. High-frequency performance projections are obtained for fabricated devices based on the extracted contact resistance.

Accuracy of Y-function methods for parameters extraction of two-dimensional FETs across different technologies

The accuracy of contact resistance values of two-dimensional field-effect transistors extracted with the \textit{Y}-function considering the impact of the intrinsic mobility degradation is evaluated here. The difference between methodologies that take this factor into account and ignore it is pointed out by a detailed analysis of the approximations of the transport model used for each extraction. In contrast to the oftenly used approach where the intrinsic mobility degradation is neglected, a \textit{Y}-function-based method considering a more complete transport model yields contact resistance values similar to reference values obtained by other intricate approaches. The latter values are more suitable also to describe experimental data of two dimensional devices of different technologies. The intrinsic mobility degradation factor of two-dimensional transistors is experimentally characterized for the first time and its impact on the device performance is described and evaluated.

Contact resistance and mobility in back-gate graphene transistors

The metal-graphene contact resistance is one of the major limiting factors toward the technological exploitation of graphene in electronic devices and sensors. High contact resistance can be detrimental to device performance and spoil the intrinsic great properties of graphene. In this paper, we fabricate back-gate graphene field-effect transistors with different geometries to study the contact and channel resistance as well as the carrier mobility as a function of gate voltage and temperature. We apply the transfer length method and the y-function method showing that the two approaches can complement each other to evaluate the contact resistance and prevent artifacts in the estimation of carrier mobility dependence on the gate-voltage. We find that the gate voltage modulates both the contact and the channel resistance in a similar way but does not change the carrier mobility. We also show that raising the temperature lowers the carrier mobility, has a negligible effect on the contact resistance, and can induce a transition from a semiconducting to a metallic behavior of the graphene sheet resistance, depending on the applied gate voltage. Finally, we show that eliminating the detrimental effects of the contact resistance on the transistor channel current almost doubles the carrier field-effect mobility and that a competitive contact resistance as low as 700 Ω·μm can be achieved by the zig-zag shaping of the Ni contact.

Accurate determination of low-field mobility in tri-gate junctionless transistors

The simple device structure of junctionless transistors (JLTs), which lack PN junctions and involve bulk-conduction-based operation, is an attractive component for the future fulfilment of Moore’s law. However, the unique bulk conduction mechanism of JLTs introduces inaccuracies in low-field mobility (μ0) extracted from conventional Y-function method. The top channel width-dependent μ0 error of tri-gate JLTs was investigated using numerical simulation and analytical modeling. This work provides important information for an accurate determination of μ0 in tri-gate JLTs.

Effects of Applied Voltages on the Charge Transport Properties in a ZnO Nanowire Field Effect Transistor.

We investigate the effect of applied gate and drain voltages on the charge transport properties in a zinc oxide (ZnO) nanowire field effect transistor (FET) through temperature- and voltage-dependent measurements. Since the FET based on nanowires is one of the fundamental building blocks in potential nanoelectronic applications, it is important to understand the transport properties relevant to the variation in electrically applied parameters for devices based on nanowires with a large surface-to-volume ratio. In this work, the threshold voltage shift due to a drain-induced barrier-lowering (DIBL) effect was observed using a Y-function method. From temperature-dependent current-voltage (I-V) analyses of the fabricated ZnO nanowire FET, it is found that space charge-limited conduction (SCLC) mechanism is dominant at low temperatures and low voltages; in particular, variable-range hopping dominates the conduction in the temperature regime from 4 to 100 K, whereas in the high-temperature regime (150–300 K), the thermal activation transport is dominant, diminishing the SCLC effect. These results are discussed and explained in terms of the exponential distribution and applied voltage-induced variation in the charge trap states at the band edge.

A Horizontal-Gate Monolayer MoS2 Transistor Based on Image Force Barrier Reduction.

Transition metal dichalcogenides (TMDCs) have received wide attention as a new generation of semiconductor materials. However, there are still many problems to be solved, such as low carrier mobility, contact characteristics between metal and two-dimensional materials, and complicated fabrication processes. In order to overcome these problems, a large amount of research has been carried out so that the performance of the device has been greatly improved. However, most of these studies are based on complicated fabrication processes which are not conducive to the improvement of integration. In view of this problem, a horizontal-gate monolayer MoS2 transistor based on image force barrier reduction is proposed, in which the gate is in the same plane as the source and drain and comparable to back-gated transistors on-off ratios up to 1 × 104 have been obtained. Subsequently, by combining the Y-Function method (YFM) and the proposed diode equivalent model, it is verified that Schottky barrier height reduction is the main reason giving rise to the observed source-drain current variations. The proposed structure of the device not only provides a new idea for the high integration of two-dimensional devices, but also provides some help for the study of contact characteristics between two-dimensional materials and metals.

Study of contact resistance with PtPc buffer layer in vertical organic field-effect transistor

The platinum phthalocyanine (PtPc) buffer layer of 0 nm–3 nm has been introduced at the interface of active layer and drain electrode in vertical organic field effect transistor (VOFET) and the performance parameters such as output current, field-effect mobility, and threshold voltage have been studied of the fabricated devices. Among all the thickness of the buffer layer, the best performance of the device has been observed by 2 nm thick buffer layer. This buffer layer may form a better contact at the active layer - drain electrode interface, thereby leading to a remarkable reduction of the contact resistance at the active layer - drain electrode interface and the contact resistance has been calculated with the help of Y-function method. Due to the limitations of a single channel length of our device structure, the Y-function method has been chosen for the calculation of contact resistance because this is a powerful method to calculate contact resistance from individual transistors. The on-off ratio, field effect mobility and trans-conductance for a fabricated VOFET with 2 nm buffer layer were increased to 3.45 × 105, 0.020 cm2 V−1s−1 and 16 μS compared to a device with 0 nm buffer layer used device structure.

Schottky-barrier thin-film transistors based on HfO2-capped InSe

Indium selenide (InSe) is an emerging two-dimensional semiconductor and a promising candidate for next generation thin film transistors (TFTs). Here, we report on Schottky barrier TFTs (SB-TFTs) in which a 0.9-nm-thick HfO2 dielectric layer encapsulates an InSe nanosheet, thus protecting the InSe-channel from the environment and reducing the Schottky-contact resistance through a dielectric dipole effect. These devices exhibit a low saturation source-drain voltage Vsat &amp;lt; 2 V and current densities of up to J = 2 mA/mm, well suited for low-power electronics. We present a detailed analysis of this type of transistor using the Y-function method from which we obtain accurate estimates of the contact resistance and field-effect mobility.

Reliable Mobility Evaluation of Organic Field-Effect Transistors With Different Contact Metals

The reliability of mobility evaluation of organic field-effect transistors (OFETs) is a serious issue because numerous overestimated and underestimated mobilities have been reported recently. A reliable approach to accurately evaluate the OFET mobility is therefore highly desirable. Here, in this letter, two commonly employed methods and the Y function method (YFM) were used to extract the mobilities of indacenodithiophene-co-benzothiadiazole (IDT-BT) OFETs with four different contact metals. The mobilities extracted by the commonly used methods varied greatly with the contact metal and channel length, whereas those extracted by the YFM were very stable and approached the intrinsic mobility of IDT-BT. Our results show that YFM is a precise approach that can be widely used to evaluate the OFET mobility.

Improving Oil-Rate Estimate in Capacitance/Resistance Modeling Using the Y-Function Method for Reservoirs Under Waterflood

Summary Capacitance/resistance modeling (CRM) is an empirical waterflood modeling technique based on the signal correlations between injection rates and gross production rates. CRM can satisfactorily estimate the gross (liquid) production rate. The oil-production-rate forecast is based on fitting the empirical oil fractional-flow model, the Leverett (1941) oil fractional-flow model, or the Koval (1963) model to the historical production data. We observed that the oil-production-rate forecast in this approach is less satisfactory. We propose a robust approach that combines CRM gross production prediction with a Buckley-Leverett displacement-theory-based waterflood analytical method—the Y-function method—to calculate the oil fraction flow and to improve the oil prediction capability. The analytical method is based on the results of the historical production performance of either an individual producer or a group of producers in a given area. By using this method, a better understanding can be developed about the production performance, such as the breakthrough time of injected water and possible operational issues, such as water channeling. The analytical model compares oil fractional flow and the cumulative gross production on the producers, yet the value of saturation is not required. As a result, the forecast of the oil-production rate becomes more convenient and straightforward. Sayarpour et al. (2009a) outlined field examples to compare the estimated oil production obtained using the current empirical oil fractional flow-model approach and the analytical Y-function method. The new method provided another effective way to calculate the oil rate in CRM. The results indicated that the new approach improved the accuracy of the oil-rate calculation and proved convenient in field applications. The objective of this study was not to regenerate the gross-rate forecast of CRM, but rather to improve the oil fractional-flow description and oil-production-rate forecast from the gross rate using the Y-function method.

Ultra-Short Pulsed Laser Annealing Effects on MoS2 Transistors with Asymmetric and Symmetric Contacts

The ultra-short pulsed laser annealing process enhances the performance of MoS2 thin film transistors (TFTs) without thermal damage on plastic substrates. However, there has been insufficient investigation into how much improvement can be brought about by the laser process. In this paper, we observed how the parameters of TFTs, i.e., mobility, subthreshold swing, Ion/Ioff ratio, and Vth, changed as the TFTs’ contacts were (1) not annealed, (2) annealed on one side, or (3) annealed on both sides. The results showed that the linear effective mobility (μeff_lin) increased from 13.14 [cm2/Vs] (not annealed) to 18.84 (one side annealed) to 24.91 (both sides annealed). Also, Ion/Ioff ratio increased from 2.27 × 10 5 (not annealed) to 3.14 × 10 5 (one side annealed) to 4.81 × 10 5 (both sides annealed), with Vth shifting to negative direction. Analyzing the main reason for the improvement through the Y function method (YFM), we found that both the contact resistance (Rc) and the channel interface resistance (Rch) improves after the pulsed laser annealings under different conditions. Moreover, the Rc enhances more dramatically than the Rch does. In conclusion, our picosecond laser annealing improves the performance of TFTs (especially, the Rc) in direct proportion to the number of annealings applied. The results will contribute to the investigation about correlations between the laser annealing process and the performance of devices.

Hysteresis Dynamics in Double-Gated n-Type WSe2 FETs With High-k Top Gate Dielectric

We propose double-gated n-type WSe2 FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO2 ALD on an Al2O3 seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe2 FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 $\mu \text{A}/\mu \text{m}$ at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 106 under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm2V−1s−1 under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS2 FETs.

Temperature-Dependent Electrical Properties of Al2O3-Passivated Multilayer MoS2 Thin-Film Transistors

It is becoming more important for electronic devices to operate stably and reproducibly under harsh environments, such as extremely low and/or high temperatures, for robust and practical applications. Here, we report on the effects of atomic-layer-deposited (ALD) aluminum oxide (Al2O3) passivation on multilayer molybdenum disulfide (MoS2) thin-film transistors (TFTs) and their temperature-dependent electrical properties, especially at a high temperature range from 293 K to 380 K. With the aid of ultraviolet-ozone treatment, an Al2O3 layer was uniformly applied to cover the entire surface of MoS2 TFTs. Our Al2O3-passivated MoS2 TFTs exhibited not only a dramatic reduction of hysteresis but also enhancement of current in output characteristics. In addition, we investigated the temperature-dependent behaviors of the TFT performance, including intrinsic carrier mobility based on the Y-function method.