Y-function Method Research Articles

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

Chemical Doping Effects of Gas Molecules on Black Phosphorus Field-Effect Transistors

Black phosphorus (BP) is a recently rediscovered layered material with outstanding optical and electrical properties. Its large adsorption energy and high surface-to-volume ratio have motivated chemical sensing and doping applications. We analyzed the charge transport properties as BP-based field-effect transistors (FETs) were chemically doped by adsorption of gas molecules. The electron-withdrawing NO2 and the electron-donating NH3 molecules were applied to observe p-doping and n-doping behaviors, respectively, in BP channel layer. Y-function method was used to extract the device parameters, allowing us to elucidate the chemical doping effects of different types of gas molecules in BP FETs. Excellent sensing ability of BP-based devices to gas molecules was also demonstrated. Our results provide a facile method to control the device properties of BP-based FET via the chemical doping.

DC Performance Variations of SOI FinFETs with Different Silicide Thickness

DC performance and the variability of n-type silicon-on-insulator dopant-segregated FinFETs with different silicide thickness (Tsili) are analyzed. DC parameters including threshold voltage, low-field-mobility-related coefficient, and parasitic resistance are extracted from Y-function method for the comparison of DC performance and variability, and the correlation analysis. All the devices show similar subthreshold characteristics, but the devices with thicker Tsili have greater threshold voltages. The devices with thicker Tsili suffer from the DC performance degradation and its greater variations because the Schottky barrier height at the NiSi/Si interface increases and fluctuates greatly. This effect is validated by greater threshold voltages, larger parasitic resistances, and high correlations among all the DC parameters for the thicker Tsili. The devices with thicker Tsili also have higher low-frequency noise because of larger parasitic resistances and their correlated mobility degradations. Therefore, the device with relatively thin Tsili is expected to have better DC performance and variability concerns.

Static and low frequency noise characterization of ultra-thin body InAs MOSFETs

A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.

Contact Effect of ReS2/Metal Interface

Rhenium disulfide (ReS2) has attracted immense interest as a promising two-dimensional material for optoelectronic devices owing to its outstanding photonic response based on its energy band gap's insensitivity to the layer thickness. Here, we theoretically calculated the electrical band structure of mono-, bi-, and trilayer ReS2 and experimentally found the work function to be 4.8 eV, which was shown to be independent of the layer thickness. We also evaluated the contact resistance of a ReS2 field-effect transistor using a Y-function method with various metal electrodes, including graphene. The ReS2 channel is a strong n-type semiconductor, thus a lower work function than that of metals tends to lead to a lower contact resistance. Moreover, the graphene electrodes, which were not chemically or physically bonded to ReS2, showed the lowest contact resistance, regardless of the work function, suggesting a significant Fermi-level pinning effect at the ReS2/metal interface. In addition, an asymmetric Schottky diode device was demonstrated using Ti or graphene for ohmic contacts and Pt or Pd for Schottky contacts. The ReS2-based transistor used in this study on the work function of ReS2 achieved the possibility of designing the next-generation nanologic devices.

Degradation pattern of black phosphorus multilayer field−effect transistors in ambient conditions: Strategy for contact resistance engineering in BP transistors

Black phosphorus (BP) has been proposed as a future optoelectronic material owing to its direct bandgap with excellent electrical performances. However, oxygen (O2) and water (H2O) molecules in an ambient condition can create undesired bubbles on the surface of the BP, resulting in hampering its excellent intrinsic properties. Here, we report the electrical degradation pattern of a mechanically exfoliated BP field–effect transistor (FET) in terms of the channel and contact, separately. Various electrical parameters such as the threshold voltage (VTH), carrier mobility (μ), contact resistance (RCT) and channel resistance (RCH) are estimated by the Y function method (YFM) with respect to time (up to 2000min). It is found that RCT reduces and then, increases with time; whereas, the behavior of RCH is vice versa in ambient conditions. We attribute these effects to oxygen doping at the contact and the surface oxidation effects on the surface of the BP, respectively.

Low Temperature Characterization of Hole Mobility in Sub-14nm Gate Length Si0.7Ge0.3 Tri-Gate pMOSFETs

We performed low temperature characterization of hole mobility in SiGe Trigate nanowires (NW) with gate length scaled down to 10nm. Trigate NWs with high-k/metal gate stack were fabricated on SOI wafers using solely optical lithography to design the wires with width down to 15nm. Drain current measurements are conducted within a cryogenic probe station enabling study on a 80K-350K temperature range. From these measurements we extracted the temperature dependence of the low field mobility μ0 for a wide range of gate lengths and NW widths using the Y-function method in order to cancel the influence of the mobility attenuation factor due to series resistances. The impact of the temperature over the mobility can be used to identify the dominant scattering mechanism in the channel. Overall, we observed that hole transport is predominantly limited by the extra scattering due to neutral defects in all devices with a gate length under 40 nm. Source/Drain implantations trace the origins of these defects. Consequently, these particular process steps should gain special care in the design of further node generation as they critically hinder charge mobility at that scale.

Effect of Al2O3 encapsulation on multilayer MoSe2 thin-film transistors

We report the effect of Al2O3 encapsulation on the device performance of multilayer MoSe2 thin-film transistors based on statistical investigation of 29 devices with a SiO2 bottom-gate dielectric. On average, Al2O3 encapsulation by atomic layer deposition increased the field-effect mobility from 10.1 cm2 V−1 s−1 to 14.8 cm2 V−1 s−1, decreased the on/off-current ratio from 8.5 × 105 to 2.3 × 105 and negatively shifted the threshold voltage from −1.1 V to −8.1 V. Calculation based on the Y-function method indicated that the enhancement of intrinsic carrier mobility occurred independently of the reduction of contact resistance after Al2O3 encapsulation. Furthermore, contrary to previous reports in the literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method for improving the carrier mobility of multilayer MoSe2 transistors, providing important implications on the application of MoSe2 and other 2D materials into high-performance transistors.

Enhanced carrier mobility of multilayer MoS2 thin-film transistors by Al2O3 encapsulation

We report the effect of Al2O3 encapsulation on the carrier mobility and contact resistance of multilayer MoS2 thin-film transistors by statistically investigating 70 devices with SiO2 bottom-gate dielectric. After Al2O3 encapsulation by atomic layer deposition, calculation based on Y-function method indicates that the enhancement of carrier mobility from 24.3 cm2 V−1 s−1 to 41.2 cm2 V−1 s−1 occurs independently from the reduction of contact resistance from 276 kΩ·μm to 118 kΩ·μm. Furthermore, contrary to the previous literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method of improving the carrier mobility of multilayer MoS2 transistors, providing important implications on the application of MoS2 and other two-dimensional materials into high-performance transistors.

Laser direct writing and inkjet printing for a sub-2 μm channel length MoS2 transistor with high-resolution electrodes

Patterns formed by the laser direct writing (LDW) lithography process are used either as channels or barriers for MoS2 transistors fabricated via inkjet printing. Silver (Ag) nanoparticle ink is printed over patterns formed on top of the MoS2 flakes in order to construct high-resolution source/drain (S/D) electrodes. When positive photoresist is used, the produced grooves are filled with inkjetted Ag ink by capillary forces. On the other hand, in the case of negative photoresist, convex barrier-like patterns are written on the MoS2 flakes and patterns, dividing the printed Ag ink into the S/D electrodes by self-alignment. LDW lithography combined with inkjet printing is applied to MoS2 thin-film transistors that exhibit moderate electrical performance such as mobility and subthreshold swing. However, especially in the linear operation regime, their features are limited by the contact effect. The Y-function method can exclude the contact effect and allow proper evaluation of the maximum available mobility and contact resistance. The presented fabrication methods may facilitate the development of cost-effective fabrication processes.

Contact resistance extraction methods for short- and long-channel carbon nanotube field-effect transistors

Three different methods for the extraction of the contact resistance based on both the well-known transfer length method (TLM) and two variants of the Y-function method have been applied to simulation and experimental data of short- and long-channel CNTFETs. While for TLM special CNT test structures are mandatory, standard electrical device characteristics are sufficient for the Y-function methods. The methods have been applied to CNTFETs with low and high channel resistance. It turned out that the standard Y-function method fails to deliver the correct contact resistance in case of a relatively high channel resistance compared to the contact resistances. A physics-based validation is also given for the application of these methods based on applying traditional Si MOSFET theory to quasi-ballistic CNTFETs.

P-109: Reduced Contact Resistance with MoOxInjection Layer for Thin Film Transistors Based on Organic Semiconductors with Deep HOMO Level

We investigated the contact resistance of the OTFTs based on dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]-thiophene (DNTT) as a representative organic semiconductors with deep HOMO level. We confirmed a dramatic decrease in the contact resistance with the MoOx injection layer by transmission line method and y-function method.

Electrical Properties of Synthesized Large-Area MoS₂ Field-Effect Transistors Fabricated with Inkjet-Printed Contacts.

We report the electrical properties of synthesized large-area monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with low-cost inkjet-printed Ag electrodes. The monolayer MoS2 film was grown by a chemical vapor deposition (CVD) method, and the top-contact Ag source/drain electrodes (S/D) were deposited onto the films using a low-cost drop-on-demand inkjet-printing process without any masks and surface treatments. The electrical characteristics of FETs were comparable to those fabricated by conventional deposition methods such as photo- or electron beam lithography. The contact properties between the S/D and the semiconductor layer were also evaluated using the Y-function method and an analysis of the output characteristic at the low drain voltage regimes. Furthermore, the electrical instability under positive gate-bias stress was studied to investigate the charge-trapping mechanism of the FETs. CVD-grown large-area monolayer MoS2 FETs with inkjet-printed contacts may represent an attractive approach for realizing large-area and low-cost thin-film electronics.

Tunable threshold voltage in solution-processed single-walled carbon nanotube thin-film transistors

We have investigated tunable threshold voltage in solution-processed single-walled carbon nanotube thin-film transistors (SWCNT TFTs) employing a simple and reproducible method of chemical encapsulation. Compared to a pristine one, SWCNT TFTs encapsulated with ammonium hydroxide (NH4OH) and nitric acid (HNO3) exhibit a negative shift and a positive shift in threshold voltage, respectively. Such results can be explained by the modification of the energy band at the interface between the source metal electrode and the SWCNT network. By using the Y-function method, we also characterized electrical properties such as field-effect mobility, threshold voltage, and contact resistance for TFTs treated with NH4OH or HNO3. The technique to favorably tune threshold voltage in solution-processed SWCNTs is significant for constituting CNT-based nanoelectronics.

Evaluation of pulsed laser annealing for flexible multilayer MoS2 transistors

To realize the proper electrical characteristics of field-effect transistors, the quality of the contact and interface must be improved because they can substantially distort the extracted mobility, especially for materials with low densities of states like molybdenum disulfide (MoS2). We show that mechanically flexible MoS2 thin-film transistors (TFTs) with selectively laser annealed source/drain electrodes achieve enhanced device performance without plastic deformation including higher field-effect mobility (from 19.59 to 45.91 cm2 V−1 s−1) in the linear regime, decreased subthreshold swing, and enhanced current saturation. Furthermore, numerical thermal simulations, measured current-voltage characteristics, and contact-free mobility extracted from the Y-function method suggest that the enhanced performance originated from a decrease in the Schottky barrier effect at the contact and an improvement of the channel interface. These results demonstrate that picosecond laser annealing can be a promising technology for building high performance flexible MoS2 TFTs in flexible/stretchable circuitry, which should be processed at low temperatures.

Extraction of Channel Length Independent Series Resistance for Deeply Scaled Metal-Oxide-Semiconductor Field-Effect Transistors

The recently developed four Rsd extraction methods from a single device, involving the constant-mobility method, the direct Id—Vgs method, the conductance method and the Y-function method, are evaluated on 32 nm n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs). It is found that Rsd achieved from the constant-mobility method exhibits the channel length independent characteristics. The L-dependent Rsd extracted from the other three methods is proven to be associated with the gate-voltage-induced mobility degradation in the extraction procedures. Based on L-dependent behaviors of Rsd, a new method is proposed for accurate series resistance extraction on deeply scaled MOSFETs.

Magnetoresistance mobility characterization in advanced FD-SOI n-MOSFETs

In this work, we applied the magnetoresistance (MR) characterization technique on n-type FD-SOI devices from a 14nm-node technology. A notable advantage of MR is that it can probe the sub-threshold region, where Coulomb scattering influence is unscreened, while classical methods are validated to the strong inversion regime. At first, we discuss the influence of series resistance depending on gate bias, gate stack and temperature in this technology. Secondly, for long channel devices, we show that Coulomb scattering plays no significant role below threshold voltage at room temperature, in spite of the presence of a high-k/metal gate stack. MR-mobility (μMR) measurements were also performed in interface coupling conditions in order to further assess the role of the high-k/metal gate stack on transport properties and to analyze back bias induced mobility variations, depending on temperature range. Finally, the comparative study of low field effective mobility (μ0) and μMR shows that critical gate length of mobility degradation can be overestimated by using μ0 at low temperature due to a lack of ability of Y-function method to capture unscreened Coulomb scattering.

Separation of surface accumulation and bulk neutral channel in junctionless transistors

The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0 ≈ 0.1 V−1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform.

Separation of interlayer resistance in multilayer MoS2 field-effect transistors

We extracted the interlayer resistance between two layers in multilayer molybdenum disulfide (MoS2) field-effect transistors by confirming that contact resistances (Rcontact) measured using the four-probe measurements were similar, within ∼30%, to source/drain series resistances (Rsd) measured using the two-probe measurements. Rcontact values obtained from gated four-probe measurements exhibited gate voltage dependency. In the two-probe measurements, the Y-function method was applied to obtain the Rsd values. By comparing those two Rcontact (∼9.5 kΩ) and Rsd (∼12.3 kΩ) values in strong accumulation regime, we found the rationality that those two values had nearly the same properties, i.e., the Schottky barrier resistances and interlayer resistances. The Rsd values of devices with two-probe source/drain electrodes exhibited thickness dependency due to interlayer resistance changes. The interlayer resistance between two layers was also obtained as ∼2.0 Ω mm.

On the mobility and contact resistance evaluation for transistors based on MoS2 or two-dimensional semiconducting atomic crystals

Contact resistance (Rc) can substantially obscure the extracted mobility based on standard transconductance or two-point conductance measurements of field-effect devices especially for low density of states materials such as MoS2 or similar atomic crystals. Currently, there exists a pressing need for a routine technique that can decouple mobility extraction from Rc. By combining experiments and analysis, we show that the Y-function method offers a robust route for evaluating the low-field mobility, threshold voltage and Rc even when the contact is a Schottky-barrier as is common in two-dimensional transistors. In addition, an independent modified transfer length method evaluation corroborates the Y-function analysis.