Magnetoresistance mobility characterization in advanced FD-SOI n-MOSFETs

Abstract

In this work, we applied the magnetoresistance (MR) characterization technique on n-type FD-SOI devices from a 14nm-node technology. A notable advantage of MR is that it can probe the sub-threshold region, where Coulomb scattering influence is unscreened, while classical methods are validated to the strong inversion regime. At first, we discuss the influence of series resistance depending on gate bias, gate stack and temperature in this technology. Secondly, for long channel devices, we show that Coulomb scattering plays no significant role below threshold voltage at room temperature, in spite of the presence of a high-k/metal gate stack. MR-mobility (μMR) measurements were also performed in interface coupling conditions in order to further assess the role of the high-k/metal gate stack on transport properties and to analyze back bias induced mobility variations, depending on temperature range. Finally, the comparative study of low field effective mobility (μ0) and μMR shows that critical gate length of mobility degradation can be overestimated by using μ0 at low temperature due to a lack of ability of Y-function method to capture unscreened Coulomb scattering.